Analog Devices AD7837SQ, AD7837BR, AD7837BQ, AD7837BN, AD7837AR Datasheet

a		LC2MOS
		Complete, Dual 12-Bit MDACs
		AD7837/AD7847

FEATURES

Two 12-Bit MDACs with Output Amplifiers 4-Quadrant Multiplication

Space-Saving 0.3", 24-Lead DIP and 24-Terminal SOIC Package

Parallel Loading Structure: AD7847

(8 + 4) Loading Structure: AD7837

APPLICATIONS

Automatic Test Equipment

Function Generation

Waveform Reconstruction

Programmable Power Supplies

Synchro Applications

GENERAL DESCRIPTION

The AD7837/AD7847 is a complete, dual, 12-bit multiplying digital-to-analog converter with output amplifiers on a monolithic CMOS chip. No external user trims are required to achieve full specified performance.

Both parts are microprocessor compatible, with high speed data latches and interface logic. The AD7847 accepts 12-bit parallel data which is loaded into the respective DAC latch using the WR input and a separate Chip Select input for each DAC. The AD7837 has a double-buffered 8-bit bus interface structure with data loaded to the respective input latch in two write operations. An asynchronous LDAC signal on the AD7837 updates the DAC latches and analog outputs.

The output amplifiers are capable of developing ± 10 V across a 2 kΩ load. They are internally compensated with low input offset voltage due to laser trimming at wafer level.

The amplifier feedback resistors are internally connected to VOUT on the AD7847.

The AD7837/AD7847 is fabricated in Linear Compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic.

A novel low leakage configuration (U.S. Patent No. 4,590,456) ensures low offset errors over the specified temperature range.

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAMS

VDD

AD7837

VREFA

VREFB

DB0

DB7

LDAC

CS

CONTROL WR LOGIC

A0

A1

MS INPUT	LS INPUT
LATCH	LATCH
4	8
DAC LATCH A
	12
DAC A

DAC B
	12
DAC LATCH B
4	8
MS INPUT	LS INPUT
LATCH	LATCH

DGND

VSS

RFBA

VOUTA

AGNDA

RFBB

VOUTB

AGNDB

		VDD
AD7847	DAC LATCH A
VREFA	DAC A	VOUTA
VREFB		AGNDA
DB0
DB11	DAC B	VOUTB

WR	CONTROL	AGNDB
CSA		DAC LATCH B
	LOGIC
CSB
	DGND	VSS

PRODUCT HIGHLIGHTS

1.The AD7837/AD7847 is a dual, 12-bit, voltage-out MDAC on a single chip. This single chip design offers considerable space saving and increased reliability over multichip designs.

2.The AD7837 and the AD7847 provide a fast versatile interface to 8-bit or 16-bit data bus structures.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2000

AD7837/AD7847–SPECIFICATIONS1 (VDD = +15 V 5%, VSS = –15 V 5%, AGNDA = AGNDB = DGND = O V. VREFA = VREFB = +10 V, RL = 2 k , CL = 100 pF [VOUT connected to RFB AD7837]. All specifications TMIN to TMAX unless otherwise noted.)

Parameter	A Version	B Version	S Version		Units	Test Conditions/Comments
STATIC PERFORMANCE
Resolution	12	12	12		Bits
Relative Accuracy2	± 1	± 1/2	± 1		LSB max
Differential Nonlinearity2	± 1	± 1	± 1		LSB max	Guaranteed Monotonic
Zero Code Offset Error2
@ +25°C	± 2	± 2	± 2		mV max	DAC Latch Loaded with All 0s
TMIN to TMAX	± 4	± 3	± 4		mV max	Temperature Coefficient = ±5 µV/°C typ
Gain Error2
@ +25°C	± 4	± 2	± 4		LSB max	DAC Latch Loaded with All 1s
TMIN to TMAX	± 5	± 3	± 5		LSB max	Temperature Coefficient = ± 2 ppm of
						FSR/°C typ
REFERENCE INPUTS					kΩ min/max	Typical Input Resistance = 10 kΩ
VREF Input Resistance	8/13	8/13	8/13
VREFA, VREFB Resistance Matching	± 2	± 2	± 2		% max	Typically ± 0.25%
DIGITAL INPUTS
Input High Voltage, VINH	2.4	2.4	2.4		V min
Input Low Voltage, VINL	0.8	0.8	0.8		V max
Input Current	± 1	± 1	± 1		µA max	Digital Inputs at 0 V and VDD
Input Capacitance3	8	8	8		pF max
ANALOG OUTPUTS					Ω typ
DC Output Impedance	0.2	0.2	0.2
Short Circuit Current	11	11	11		mA typ	VOUT Connected to AGND
POWER REQUIREMENTS4
VDD Range	14.25/15.75	14.25/15.75	14.25/15.75		V min/max
VSS Range	–14.25/–15.75	–14.25/–15.75	–14.25/–15.75		V min/max
Power Supply Rejection
∆Gain/∆VDD	± 0.01	± 0.01	± 0.01		% per % max	VDD = 15 V ± 5%, VREF = –10 V
∆Gain/∆VSS	± 0.01	± 0.01	± 0.01		% per % max	VSS = –15 V ± 5%, VREF = +10 V
IDD	8	8	8		mA max	Outputs Unloaded. Inputs at Thresholds.
						Typically 5 mA
ISS	6	6	6		mA max	Outputs Unloaded. Inputs at Thresholds.
						Typically 3 mA
AC CHARACTERISTICS2, 3					µs typ	Settling Time to Within ± 1/2 LSB of Final
Voltage Output Settling Time	3	3	3
	5	5	5		µs max	Value. DAC Latch Alternately Loaded
					V/µs typ	with All 0s and All 1s
Slew Rate	11	11	11
Digital-to-Analog Glitch Impulse	10	10	10		nV secs typ	1 LSB Change Around Major Carry
Channel-to-Channel Isolation
VREFA to VOUTB	–95	–95	–95		dB typ	VREFA = 20 V p-p, 10 kHz Sine Wave.
						DAC Latches Loaded with All 0s
VREFB to VOUTA	–95	–95	–95		dB typ	VREFB = 20 V p-p, 10 kHz Sine Wave.
						DAC Latches Loaded with All 0s
Multiplying Feedthrough Error	–90	–90	–90		dB typ	VREF = 20 V p-p, 10 kHz Sine Wave.
						DAC Latch Loaded with All 0s
Unity Gain Small Signal BW	750	750	750		kHz typ	VREF = 100 mV p-p Sine Wave. DAC
						Latch Loaded with All 1s
Full Power BW	175	175	175		kHz typ	VREF = 20 V p-p Sine Wave. DAC
						Latch Loaded with All 1s
Total Harmonic Distortion	–88	–88	–88		dB typ	VREF = 6 V rms, 1 kHz. DAC Latch
						Loaded with All 1s
Digital Crosstalk	1	1	1		nV secs typ	Code Transition from All 0s to All 1s and
Output Noise Voltage @ +25°C						Vice Versa
					µV rms typ	See Typical Performance Graphs
(0.1 Hz to 10 Hz)	2	2	2			Amplifier Noise and Johnson Noise of RFB
Digital Feedthrough	1	1	1		nV secs typ

NOTES

1Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C. 2See Terminology.

3Guaranteed by design and characterization, not production tested.

4The Devices are functional with VDD/VSS = ± 12 V (See typical performance graphs.).

Specifications subject to change without notice.

–2–

REV. C

				AD7837/AD7847
TIMING CHARACTERISTICS1, 2, 3		(VDD = +15 V 5%, VSS = –15 V 5%, AGNDA = AGNDB = DGND = O V)
	Limit at TMIN, TMAX
Parameter	(All Versions)		Unit	Conditions/Comments
t1	0		ns min	CS to WR Setup Time
t2	0		ns min	CS to WR Hold Time
t3	30		ns min	WR Pulsewidth
t4	80		ns min	Data Valid to WR Setup Time
t5	0		ns min	Data Valid to WR Hold Time
t64	0		ns min	Address to WR Setup Time
t74	0		ns min	Address to WR Hold Time
t84	50		ns min	LDAC Pulsewidth

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 3 and 5.

3Guaranteed by design and characterization, not production tested.

4AD7837 only.

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to DGND, AGNDA, AGNDB . . .	. . .	. –0.3 V to +17 V
VSS1 to DGND, AGNDA, AGNDB . . .	. . .	. +0.3 V to –17 V
VREFA, VREFB to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3			V
AGNDA, AGNDB to DGND . . . . . . .	–0.3 V to VDD + 0.3 V
VOUTA2, VOUTB2 to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3			V
RFBA3, RFBB3 to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3			V
Digital Inputs to DGND . . . . . . . . . . .	–0.3 V to VDD + 0.3		V
Operating Temperature Range	. . . –40°C to +85°C
Commercial/Industrial (A, B Versions)
Extended (S Version) . . . . . . . . . . . . .	. . .	–55°C to +125°C
Storage Temperature Range . . . . . . . . .	. . .	–65°C to +150°C
Lead Temperature (Soldering, 10 secs) .	. . . .	. . . . . . . . 300°C
Power Dissipation (Any Package) to +75°C .		. . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . .	. . . .	. . . . 10 mW/°C

NOTES

1If VSS is open circuited with VDD and either AGND applied, the VSS pin will float positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a Schottky diode connected between VSS and AGND (cathode to AGND) ensures the Maximum Ratings will be observed.

2The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded.

3AD7837 only.

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time.

ORDERING GUIDE

	Temperature	Relative	Package
Model1	Range	Accuracy	Option2
AD7837AN	–40°C to +85°C	±1 LSB	N-24
AD7837BN	–40°C to +85°C	±1/2 LSB	N-24
AD7837AR	–40°C to +85°C	±1 LSB	R-24
AD7837BR	–40°C to +85°C	±1/2 LSB	R-24
AD7837AQ	–40°C to +85°C	±1 LSB	Q-24
AD7837BQ	–40°C to +85°C	±1/2 LSB	Q-24
AD7837SQ	–55°C to +125°C	±1 LSB	Q-24
AD7847AN	–40°C to +85°C	±1 LSB	N-24
AD7847BN	–40°C to +85°C	±1/2 LSB	N-24
AD7847AR	–40°C to +85°C	±1 LSB	R-24
AD7847BR	–40°C to +85°C	±1/2 LSB	R-24
AD7847AQ	–40°C to +85°C	±1 LSB	Q-24
AD7847BQ	–40°C to +85°C	±1/2 LSB	Q-24
AD7847SQ	–55°C to +125°C	±1 LSB	Q-24

NOTES

1To order MIL-STD-883, Class B processed parts, add /883B to part number. 2N = Plastic DIP; Q = Cerdip; R = SOIC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–3–

AD7837/AD7847

TERMINOLOGY

Relative Accuracy (Linearity)

Relative accuracy, or endpoint linearity, is a measure of the maximum deviation of the DAC transfer function from a straight line passing through the endpoints. It is measured after allowing for zero and full-scale errors and is expressed in LSBs or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB or less over the operating temperature range ensures monotonicity.

Zero Code Offset Error

Zero code offset error is the error in output voltage from VOUTA or VOUTB with all 0s loaded into the DAC latches. It is due to a combination of the DAC leakage current and offset errors in the

output amplifier.

Gain Error

Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded. It does not include offset error.

Total Harmonic Distortion

This is the ratio of the root-mean-square (rms) sum of the harmonics to the fundamental, expressed in dBs.

Multiplying Feedthrough Error

This is an ac error due to capacitive feedthrough from the VREF

input to VOUT of the same DAC when the DAC latch is loaded with all 0s.

Channel-to-Channel Isolation

This is an ac error due to capacitive feedthrough from the VREF

input on one DAC to VOUT on the other DAC. It is measured with the DAC latches loaded with all 0s.

Digital Feedthrough

Digital feedthrough is the glitch impulse injected from the digital inputs to the analog output when the data inputs change state, but the data in the DAC latches is not changed.

For the AD7837, it is measured with LDAC held high. For the AD7847, it is measured with CSA and CSB held high.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in digital code on the DAC latch of the other converter. It is specified in nV secs.

Digital-to-Analog Glitch Impulse

This is the voltage spike that appears at the output of the DAC when the digital code changes, before the output settles to its final value. The energy in the glitch is specified in nV secs and is measured for a 1 LSB change around the major carry transition (0111 1111 1111 to 1000 0000 0000 and vice versa).

Unity Gain Small Signal Bandwidth

This is the frequency at which the small signal voltage output from the output amplifier is 3 dB below its dc level. It is measured with the DAC latch loaded with all 1s.

Full Power Bandwidth

This is the maximum frequency for which a sinusoidal input signal will produce full output at rated load with a distortion less than 3%. It is measured with the DAC latch loaded with all 1s.

		AD7837 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)
Pin	Mnemonic	Description
1	CS	Chip Select. Active low logic input. The device is selected when this input is active.
2	RFBA	Amplifier Feedback Resistor for DAC A.
3	VREFA	Reference Input Voltage for DAC A. This may be an ac or dc signal.
4	VOUTA	Analog Output Voltage from DAC A.
5	AGNDA	Analog Ground for DAC A.
6	VDD	Positive Power Supply.
7	VSS	Negative Power Supply.
8	AGNDB	Analog Ground for DAC B.
9	VOUTB	Analog Output Voltage from DAC B.
10	VREFB	Reference Input Voltage for DAC B. This may be an ac or dc signal.
11	DGND	Digital Ground. Ground reference for digital circuitry.
12	RFBB	Amplifier Feedback Resistor for DAC B.
13	WR	Write Input. WR is an active low logic input which is used in conjunction with CS, A0 and A1 to
		write data to the input latches.
14	LDAC	DAC Update Logic Input. Data is transferred from the input latches to the DAC latches when LDAC
		is taken low.
15	A1	Address Input. Most significant address input for input latches (see Table II).
16	A0	Address Input. Least significant address input for input latches (see Table II).
17–20	DB7–DB4	Data Bit 7 to Data Bit 4.
21–24	DB3–DB0	Data Bit 3 to Data Bit 0 (LSB) or Data Bit 11 (MSB) to Data Bit 8.

–4–

REV. C