Analog Devices AD7829BRU, AD7829BR, AD7829BN, AD7822BRU, AD7822BR Datasheet

a		3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel
		Sampling ADCs
		AD7822/AD7825/AD7829

FEATURES

8-Bit Half-Flash ADC with 420 ns Conversion Time 1, 4 and 8 Single-Ended Analog Input Channels

Available with Input Offset Adjust On-Chip Track-and-Hold

SNR Performance Given for Input Frequencies Up to 10 MHz

On-Chip Reference (2.5 V)

Automatic Power-Down at the End of Conversion Wide Operating Supply Range

3 V 10% and 5 V 10%

Input Ranges

0 V to 2 V p-p, VDD = 3 V 10% 0 V to 2.5 V p-p, VDD = 5 V 10%

Flexible Parallel Interface with EOC Pulse to Allow Stand-Alone Operation

APPLICATIONS

Data Acquisition Systems, DSP Front Ends

Disk Drives

Mobile Communication Systems, Subsampling

Applications

FUNCTIONAL BLOCK DIAGRAM

		CONVST EOC		A0* A1* A2* PD*			VDD
			CONTROL				COMP
				LOGIC
							2.5V
							REF
VIN1							BUF	VREFIN / OUT
V	*
IN2
VIN3*		INPUT			8-BIT
VIN4*			T/H		HALF
VIN5*		MUX			FLASH
					ADC		PARALLEL	DB7
VIN6*
								DB0
VIN7*							PORT
VIN8*
			VMID		AGND	DGND	CS RD
		*A0, A1		AD7825/AD7829
		*A2		AD7829
		*PD		AD7822/AD7825
		*VIN2 TO VIN4		AD7825/AD7829
		*VIN4 TO VIN8		AD7829

GENERAL DESCRIPTION

The AD7822, AD7825, and AD7829 are high speed, 1-, 4-, and 8-channel, microprocessor-compatible, 8-bit analog-to-digital converters with a maximum throughput of 2 MSPS. The AD7822, AD7825, and AD7829 contain an on-chip reference of 2.5 V (2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash ADC and a high speed parallel interface. The converters can operate from a single 3 V ± 10% and 5 V ± 10% supply.

The AD7822, AD7825, and AD7829 combine the convert start and power-down functions at one pin, i.e., the CONVST pin.

This allows a unique automatic power-down at the end of a conversion to be implemented. The logic level on the CONVST

pin is sampled after the end of a conversion when an EOC (End of Conversion) signal goes high, and if it is logic low at that point, the ADC is powered down. The AD7822 and AD7825 also have a separate power-down pin. (See Operating Modes section of the data sheet.)

The parallel interface is designed to allow easy interfacing to microprocessors and DSPs. Using only address decoding logic, the parts are easily mapped into the microprocessor address space. The EOC pulse allows the ADCs to be used in a standalone manner. (See Parallel Interface section of the data sheet.)

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The AD7822 and AD7825 are available in a 20-/24-lead 0.3" wide, plastic dual-in-line package (DIP), a 20-/24-lead small outline IC (SOIC) and a 20-/24-lead thin shrink small outline package (TSSOP). The AD7829 is available in a 28-lead 0.6" wide, plastic dual-in-line package (DIP), a 28-lead small outline IC (SOIC) and in a 28-lead thin shrink small outline package (TSSOP).

PRODUCT HIGHLIGHTS

1.Fast Conversion Time

The AD7822, AD7825, and AD7829 have a conversion time of 420 ns. Faster conversion times maximize the DSP processing time in a real-time system.

2.Analog Input Span Adjustment

The VMID pin allows the user to offset the input span. This feature can reduce the requirements of single-supply op amps and take into account any system offsets.

3.FPBW (Full Power Bandwidth) of Track-and-Hold

The track-and-hold amplifier has an excellent high-frequency performance. The AD7822, AD7825, and AD7829 are capable of converting full-scale input signals up to a frequency of 10 MHz. This makes the parts ideally suited to subsampling applications.

4.Channel Selection

Channel selection is made without the necessity of writing to the part.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2001

AD7822/AD7825/AD7829–SPECIFICATIONS(VDD = 3 V 10%, VDD = 5 V 10%, GND = 0 V,

VREF IN/OUT = 2.5 V. All specifications –40 C to +85 C unless otherwise noted.)

Parameter	Version B	Unit	Test Condition/Comment
DYNAMIC PERFORMANCE			fIN = 30 kHz. fSAMPLE = 2 MHz
Signal to (Noise + Distortion) Ratio1	48	dB min
Total Harmonic Distortion1	–55	dB max
Peak Harmonic or Spurious Noise1	–55	dB max
Intermodulation Distortion1			fa = 27.3 kHz, fb = 28.3 kHz
2nd Order Terms	–65	dB typ
3rd Order Terms	–65	dB typ
Channel-to-Channel Isolation1	–70	dB typ	fIN = 20 kHz
DC ACCURACY
Resolution	8	Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed	8	Bits
Integral Nonlinearity (INL)1	±0.75	LSB max
Differential Nonlinearity (DNL)1	±0.75	LSB max
Gain Error1	±2	LSB max
Gain Error Match1	±0.1	LSB typ
Offset Error1	±1	LSB max
Offset Error Match1	±0.1	LSB typ
ANALOG INPUTS2			See Analog Input Section
VDD = 5 V ± 10%			Input Voltage Span = 2.5 V
VIN1 to VIN8 Input Voltage	VDD	V max
	0	V min
VMID Input Voltage	VDD – 1.25	V max	Default VMID = 1.25 V
VDD = 3 V ± 10%	1.25	V min
			Input Voltage Span = 2 V
VIN1 to VIN8 Input Voltage	VDD	V max
	0	V min
VMID Input Voltage	VDD – 1	V max	Default VMID = 1 V
	1	V min
VIN Input Leakage Current	±1	µA max
VIN Input Capacitance	15	pF max
VMID Input Impedance	6	kΩ typ
REFERENCE INPUT
VREF IN/OUT Input Voltage Range	2.55	V max	2.5 V + 2%
	2.45	V min	2.5 V – 2%
Input Current	1	µA typ
	100	µA max
ON-CHIP REFERENCE	±50		Nominal 2.5 V
Reference Error		mV max
Temperature Coefficient	50	ppm/°C typ
LOGIC INPUTS			VDD = 5 V ± 10%
Input High Voltage, VINH	2.4	V min
Input Low Voltage, VINL	0.8	V max	VDD = 5 V ± 10%
Input High Voltage, VINH	2	V min	VDD = 3 V ± 10%
Input Low Voltage, VINL	0.4	V max	VDD = 3 V ± 10%
Input Current, IIN	±1	µA max	Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN	10	pF max
LOGIC OUTPUTS			ISOURCE = 200 µA
Output High Voltage, VOH
	4	V min	VDD = 5 V ± 10%
	2.4	V min	VDD = 3 V ± 10%
Output Low Voltage, VOL			ISINK = 200 µA
	0.4	V max	VDD = 5 V ± 10%
	0.2	V max	VDD = 3 V ± 10%
High Impedance Leakage Current	±1	µA max
High Impedance Capacitance	10	pF max

–2–

REV. B

			AD7822/AD7825/AD7829
Parameter	Version B	Unit	Test Condition/Comment
CONVERSION RATE
Track/Hold Acquisition Time	200	ns max	See Functional Description Section
Conversion Time	420	ns max
POWER SUPPLY REJECTION
VDD ± 10%	±1	LSB max
POWER REQUIREMENTS			5 V ± 10%. For Specified Performance
VDD	4.5	V min
	5.5	V max	3 V ± 10%. For Specified Performance
VDD	2.7	V min
	3.3	V max
IDD
Normal Operation	12	mA max	8 mA Typically
Power-Down	5	A max	Logic Inputs = 0 V or VDD
	0.2	A typ
Power Dissipation			VDD = 3 V
Normal Operation	36	mW max	Typically 24 mW
Power-Down
200 kSPS	9.58	mW typ
500 kSPS	23.94	mW typ

NOTES

1See Terminology section of this data sheet.

2Refer to the Analog Input section for an explanation of the Analog Input(s). Specifications subject to change without notice.

200 A	IOL
TO	2.1V
OUTPUT
PIN
CL
50pF
200 A	IOH

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

ORDERING GUIDE

	Linearity	Package	Package
Model	Error	Description	Option
AD7822BN	±0.75 LSB	Plastic DIP	N-20
AD7822BR	±0.75 LSB	Small Outline IC	R-20
AD7822BRU	±0.75 LSB	Thin Shrink Small	RU-20
	±0.75 LSB	Outline (TSSOP)
AD7825BN		Plastic DIP	N-24
AD7825BR	±0.75 LSB	Small Outline IC	R-24
AD7825BRU	±0.75 LSB	Thin Shrink Small	RU-24
	±0.75 LSB	Outline (TSSOP)
AD7829BN		Plastic DIP	N-28
AD7829BR	±0.75 LSB	Small Outline IC	R-28
AD7829BRU	±0.75 LSB	Thin Shrink Small	RU-28
		Outline (TSSOP)

REV. B

–3–

AD7822/AD7825/AD7829

TIMING CHARACTERISTICS1, 2 (VREF IN/OUT = 2.5 V. All specifications –40 C to +85 C unless otherwise noted.)

Parameter	5 V 10%	3 V 10%	Unit	Conditions/Comments
t1	420	420	ns max	Conversion Time.
t2	20	20	ns min	Minimum CONVST Pulsewidth.
t3	30	30	ns min	Minimum time between the rising edge of RD and next falling edge of convert start.
t4	110	110	ns max	EOC Pulsewidth.
	70	70	ns min
t5	10	10	ns max	RD rising edge to EOC pulse high.
t6	0	0	ns min	CS to RD setup time.
t7	0	0	ns min	CS to RD hold time.
t8	30	30	ns min	Minimum RD Pulsewidth.
t93	10	20	ns max	Data access time after RD low.
t104	5	5	ns min	Bus relinquish time after RD high.
	20	20	ns max
t11	10	10	ns min	Address setup time before falling edge of RD.
t12	15	15	ns min	Address hold time after falling edge of RD.
t13	200	200	ns min	Minimum time between new channel selection and convert start.
tPOWER UP	25	25	µs typ	Power-up time from rising edge of CONVST using on-chip reference.
tPOWER UP	1	1	µs max	Power-up time from rising edge of CONVST using external 2.5 V reference.

NOTES

1Sample tested to ensure compliance.

2See Figures 20, 21, and 22.

3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V DD = 5 V ± 10%, and time required for an output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.

4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 10, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . .	. . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . .	. . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
VIN1 to VIN8 . . . . . . . . . . . . . . . . . . .	–0.3 V to VDD + 0.3 V
Reference Input Voltage to AGND . . .	–0.3 V to VDD + 0.3 V
VMID Input Voltage to AGND . . . . . . .	–0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . .	–0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . .	–0.3 V to VDD + 0.3 V
Operating Temperature Range	–40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . .
Storage Temperature Range . . . . . . . . . .	. . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . .	. . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation .	. . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . .	. . . . . . . . . 105°C/W
Lead Temperature, (Soldering, 10 sec)	. . . . . . . . . . . 260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7822/AD7825/AD7829 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. B

	AD7822/AD7825/AD7829
	PIN FUNCTION DESCRIPTIONS
Mnemonic	Description
VIN1 to VIN8	Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
	analog input channels respectively. The inputs have an input span of 2.5 V and 2 V depending on the sup-
	ply voltage (VDD). This span may be centered anywhere in the range AGND to VDD using the VMID Pin. The
	default input range (VMID unconnected) is AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V
	± 10%). See Analog Input section of the data sheet for more information.
VDD	Positive supply voltage, 3 V ± 10% and 5 V ± 10%.
AGND	Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
DGND	Digital Ground. Ground reference for digital circuitry.
CONVST	Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of
	this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
	mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of
	a conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Modes section
	of the data sheet.)
EOC	Logic Output. The End of Conversion signal indicates when a conversion has finished. The signal can be used
	to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Inter-
	face section of this data sheet.)
CS	Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829.
	This is necessary if the ADC is sharing a common data bus with another device.
PD	Logic Input. The Power-Down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low
	places the AD7822 and AD7825 in Power-Down mode. The ADCs will power up when PD is brought logic
	high again.
RD	Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and
	drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic
	low to enable the data bus.
A0–A2	Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the
	RD signal goes low.
DB0–DB7	Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when
	both RD and CS go active low.
VREF IN/OUT	Analog Input and Output. An external reference can be connected to the AD7822, AD7825, and AD7829 at this
	pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be
	left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 F capacitor.
	PIN CONFIGURATIONS
	DIP/SOIC/TSSOP

	DB2	1				20	DB3
	DB1	2				19	DB4
	DB0	3				18	DB5
	CONVST	4				17	DB6
	CS	5	AD7822			16	DB7
			TOP VIEW
	RD	6				15	AGND
			(Not to Scale)
	DGND	7				14	V
							DD
	EOC	8				13	VREF IN/OUT
	PD	9				12	VMID
	NC	10				11	VIN1

NC = NO CONNECT

DB2	1				24	DB3
DB1	2				23	DB4
DB0	3				22	DB5
CONVST	4				21	DB6
CS	5	AD7825			20	DB7
RD	6	TOP VIEW			19	AGND
		(Not to Scale)			18
DGND	7					V
						DD
EOC	8				17	VREF IN/OUT
A1	9				16	VMID
A0	10				15	VIN1
PD	11				14	VIN2
					13
VIN4	12					VIN3

	DB2	1				28 DB3
	DB1	2				27	DB4
	DB0	3				26	DB5
	CONVST	4				25	DB6
	CS	5				24	DB7
	RD	6				23	AGND
			AD7829
	DGND	7				22	VDD
			TOP VIEW
	EOC	8	(Not to Scale)			21	VREF IN/OUT
	A2	9				20	V
							MID
	A1	10				19	VIN1
	A0	11				18	VIN2
	VIN8
		12				17	VIN3
	VIN7	13				16	VIN4
	VIN6	14				15	VIN5

REV. B

–5–

AD7822/AD7825/AD7829

TERMINOLOGY

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for an 8-bit converter, this is 50 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7822/AD7825/AD7829 it is defined as:

V 2 +V 2 +V 2 +V 2 +V 2

= 2 3 4 5 6

THD (dB) 20 log

V1

where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

The AD7822/AD7825/AD7829 are tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 20 kHz sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. The figure given is the worst case across all four or eight channels of the AD7825 and AD7829, respectively.

Relative Accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

The deviation of the 128th code transition (01111111) to (10000000) from the ideal, i.e., VMID.

Offset Error Match

The difference in offset error between any two channels.

Zero-Scale Error

The deviation of the first code transition (00000000) to (00000001) from the ideal, i.e., VMID – 1.25 V + 1 LSB (VDD = 5 V ± 10%), or VMID – 1.0 V + 1 LSB (VDD = 3 V ± 10%).

Full-Scale Error

The deviation of the last code transition (11111110) to (11111111) from the ideal, i.e., VMID + 1.25 V – 1 LSB (VDD = 5 V ± 10%), or VMID + 1.0 V – 1 LSB (VDD = 3 V ± 10%).

Gain Error

The deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Track/Hold Acquisition Time

The time required for the output of the track/hold amplifier to reach its final value, within ±1/2 LSB, after the point at which

the track/hold returns to track mode. This happens approximately 120 ns after the falling edge of CONVST.

It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected VIN input of the AD7822/ AD7825/AD7829. It means that the user must wait for the duration of the track/hold acquisition time after a channel change/step input change to VIN before starting another conversion, to ensure that the part operates to specification.

PSR (Power Supply Rejection)

Variations in power supply will affect the full-scale transition, but not the converter’s linearity. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value.

CIRCUIT DESCRIPTION

The AD7822, AD7825, and AD7829 consist of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. These devices use a half-flash conversion technique where one 4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash ADC contains a sampling capacitor followed by fifteen comparators that compare the unknown input to a reference ladder to achieve a 4-bit result. This first flash, i.e., coarse conversion, provides the 4 MSBs. For a full 8-bit reading to be realized, a second flash, i.e., a fine conversion, must be performed to provide the 4 LSBs. The 8-bit word is then placed on the data output bus.

–6–

REV. B