Analog Devices AD7376AN50, AD7376AN1M, AD7376AN100, AD7376AN10, AD7376ARU50 Datasheet

a		615 V Operation
		Digital Potentiometer
		AD7376*
	FEATURES	FUNCTIONAL BLOCK DIAGRAM

128 Position

Potentiometer Replacement 10 kV, 50 kV, 100 kV, 1 MV

Power Shutdown: Less than 1 mA

3-Wire SPI Compatible Serial Data Input

+5 V to +30 V Single Supply Operation 65 V to 615 V Dual Supply Operation

Midscale Preset

APPLICATIONS

Mechanical Potentiometer Replacement

Instrumentation: Gain, Offset Adjustment

Programmable Voltage-to-Current Conversion

Programmable Filters, Delays, Time Constants

Line Impedance Matching

Power Supply Adjustment

GENERAL DESCRIPTION

The AD7376 provides a single channel, 128-position digitallycontrolled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment applications where a combination of high voltage with a choice between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The AD7376 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ or 1 MΩ has a nominal temperature coefficient of –300 ppm/°C.

The VR has its own VR latch which holds its programmed resistance value. The VR latch is updated from an internal serial-to- parallel shift register which is loaded from a standard 3-wire serial-input digital interface. Seven data bits make up the data word clocked into the serial data input register (SDI). Only the last seven bits of the data word loaded are transferred into the 7-bit VR latch when the CS strobe is returned to logic high. A serial data output pin (SDO) at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.

The reset (RS) pin forces the wiper to the midscale position by loading 40H into the VR latch. The SHDN pin forces the resistor

*Patent Number: 5495245

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	AD7376				VDD
SDO	Q				A
		7-BIT
			7	7-BIT	7
		SERIAL		LATCH	W
	REGISTER				B
SDI	D
		CK		R	SHDN
CLK					VSS
CS
	GND			RS	SHDN

to an end-to-end open circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When shutdown is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown as long as power to VDD is not removed. The digital interface is still active in shutdown so that code changes can be made that will produce a new wiper position when the device is taken out of shutdown.

The AD7376 is available in both surface mount (SOL-16) and the 14-lead plastic DIP package. For ultracompact solutions selected models are available in the thin TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C. For operation at lower supply voltages (+3 V to +5 V), see the AD8400/AD8402/ AD8403 products.

SDI

1

DX

DX

(DATA IN)

0

tDS

SDO

1

tDH

D'X

D'X

(DATA OUT) 0

tPD_MAX

1

tCH

tCS1

CLK

0

tCSH0

tCL

tCSH

1

tCSS

CS

0

tCSW

VDD

tS

VOUT

0V

61 LSB ERROR BAND

61 LSB

Figure 1. Detail Timing Diagram

The last seven data bits clocked into the serial input register will be transferred to the VR 7-bit latch when CS returns to logic high. Extra data bits are ignored.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 1997

AD7376–SPECIFICATIONS

	(VDD/VSS = 615 V 6 10% or 6 5 V 6 10%, VA = +VDD, VB = VSS/0 V, –408C < TA < +858C
ELECTRICAL CHARACTERISTICS unless otherwise noted.)
Parameter	Symbol	Conditions	Min	Typ1	Max	Units
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)				± 0.25
Resistor Differential NL2	R-DNL	RWB, VA = NC	–1		+1	LSB
Resistor Nonlinearity2	R-INL	RWB, VA = NC	–1	± 0.5	+1	LSB
Nominal Resistor Tolerance	DR	TA = +25°C	–30		30	%
Resistance Temperature Coefficient	RAB/DT	VAB = VDD, Wiper = No Connect		–300		ppm/°C
Wiper Resistance	RW	IW = ± 15 V/RNOMINAL		120	200	W
Wiper Resistance	RW	IW = ± 5 V/RNOMINAL		200		W
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Resolution	N		7	± 0.5		Bits
Integral Nonlinearity3	INL		–1		+1	LSB
Differential Nonlinearity3	DNL		–1	± 0.1	+1	LSB
Voltage Divider Temperature Coefficient	DVW/DT	Code = 40H		5		ppm/°C
Full-Scale Error	VWFSE	Code = 7FH	–2	–0.5	+0	LSB
Zero-Scale Error	VWZSE	Code = 00H	0	+0.5	+1	LSB
RESISTOR TERMINALS
Voltage Range4	VA, B, W		VSS		VDD	V
Capacitance5 A, B	CA, B	f = 1 MHz, Measured to GND, Code = 40H		45		pF
Capacitance5 W	CW	f = 1 MHz, Measured to GND, Code = 40H		60		pF
Shutdown Supply Current6	IA_SD	VA = VDD, VB = 0 V, SHDN = 0		0.01	1	mA
Shutdown Wiper Resistance	RW_SD	VA = VDD, VB = 0 V, SHDN = 0, VDD = +15 V		170	400	W
Common-Mode Leakage	ICM	VA = VB = VW		1		nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High	VIH	VDD = +5 V or +15 V	2.4			V
Input Logic Low	VIL	VDD = +5 V or +15 V			0.8	V
Output Logic High	VOH	RL = 2.2 kW to +5 V	4.9			V
Output Logic Low7	VOL	IOL = 1.6 mA, VLOGIC = +5 V, VDD = +15 V			0.4	V
Input Current	IIL	VIN = 0 V or +15 V			± 1	mA
Input Capacitance5	CIL			5		pF
POWER SUPPLIES			± 4.5		± 16.5
Power Supply Range	VDD/VSS	Dual Supply Range				V
Power Supply Range	VDD	Single Supply Range, VSS = 0	4.5		28	V
Supply Current	IDD	VIH = +5 V or VIL = 0 V, VDD = +5 V		0.0001	0.01	mA
Supply Current	IDD	VIH = +5 V or VIL = 0 V, VDD = +15 V		0.75	2	mA
Supply Current	ISS	VIH = +5 V or VIL = 0 V, VSS = –5 V or –15 V		0.02	0.1	mA
Power Dissipation8	PDISS	VIH = +5 V or VIL = 0 V, VDD = +15 V, VSS = –15 V		11	30	mW
Power Supply Sensitivity	PSS	DVDD = +5 V ± 10%, or DVSS = –5 V ± 10%		0.05	0.15	%/%
	PSS	DVDD = +15 V ± 10% or DVSS = –15 V ± 10%		0.01	0.02	%/%
DYNAMIC CHARACTERISTICS5, 9, 10		RAB = 10 kW, Code = 40H
Bandwidth –3 dB	BW_10K			520		kHz
Bandwidth –3 dB	BW_50K	RAB = 50 kW, Code = 40H		125		kHz
Bandwidth –3 dB	BW_100K	RAB = 100 kW, Code = 40H		60		kHz
Total Harmonic Distortion	THDW	VA = 1 V rms, VB = 0 V, f = 1 kHz		0.005		%
VW Settling Time	tS	VA = 10 V, VB = 0 V, ±1 LSB Error Band		4		ms
Resistor Noise Voltage	eN_WB	RWB = 25 kW, f = 1 kHz, RS = 0		14		nVÖHz
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 5, 11])
Input Clock Pulsewidth	tCH, tCL	Clock Level High or Low	120			ns
Data Setup Time	tDS		30			ns
Data Hold Time	tDH	RL = 2.2 kW, CL < 20 pF	20			ns
CLK to SDO Propagation Delay12	tPD		10		100	ns
CS Setup Time	tCSS		120			ns
CS High Pulsewidth	tCSW		150			ns
Reset Pulsewidth	tRS		120			ns
CLK Rise to CS Rise Hold Time	tCSH		120			ns
CS Rise to Clock Rise Setup	tCS1		120			ns

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AD7376

NOTES

1Typicals represent average readings at +25°C, VDD = +15 V, and VSS = –15 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit.

3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit.

4Resistor terminals A, B, W have no limitations on polarity with respect to each other. 5Guaranteed by design and not subject to production test.

6Measured at the A terminal. A terminal is open circuit in shutdown mode. 7IOL = 200 μA for the 50 kΩ version operating at VDD = +5 V.

8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

9Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption.

10All dynamic characteristics use VDD = +15 V and VSS = –15 V.

11See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both VDD = +5 V or +15 V.

12Propagation delay depends on value of VDD, RL and CL see Applications section. Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C, unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . .	.	. . . –0.3 V, +30	V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . .	.	. +0.3 V, –16.5 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . .	.	. . –0.3 V, +44	V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . .	.	. . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX . . . . . . . . . . . .	.	. . . . . . ±20 mA
Digital Input Voltages to GND . . . . . . . . . .		0 V, VDD + 0.3	V
Digital Output Voltage to GND . . . . . . . . .	.	. . . . 0 V, +30	V
Operating Temperature Range . . . . . . . . . .	.	–40°C to +85°C
Maximum Junction Temperature (TJ MAX)		. . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .		–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . .	.	. . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . .	(TJ MAX – TA)/θJA
Thermal Resistance θJA		92°C/W
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . .	.
SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . .	.	. . . . . 120°C/W
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . .	.	. . . . . 240°C/W

PIN CONFIGURATIONS

PDIP & TSSOP-14

SOL-16

A
	1		14	W
B
	2		13	NC
VSS	3	AD7376	12	VDD
GND	4	TOP VIEW	11	SDO
		(Not to Scale)
CS	5		10	SHDN
				SDI
RS	6		9
CLK				NC
	7		8

NC = NO CONNECT

A	1		16	W
B	2		15	NC
VSS	3		14	VDD
		AD7376
GND	4		13	SDO
		TOP VIEW
CS	5	(Not to Scale)	12	SHDN
				SDI
RS	6		11
CLK				NC
	7		10
NC				NC
	8		9

NC = NO CONNECT

ORDERING GUIDE

		Temperature	Package	Package
Model	kV	Range	Description	Options
AD7376AN10	10	–40°C to +85°C	PDIP-14	N-14
AD7376AR10	10	–40°C to +85°C	SOL-16	R-16
AD7376ARU10	10	–40°C to +85°C	TSSOP-14	RU-14
AD7376AN50	50	–40°C to +85°C	PDIP-14	N-14
AD7376AR50	50	–40°C to +85°C	SOL-16	R-16
AD7376ARU50	50	–40°C to +85°C	TSSOP-14	RU-14
AD7376AN100	100	–40°C to +85°C	PDIP-14	N-14
AD7376AR100	100	–40°C to +85°C	SOL-16	R-16
AD7376ARU100	100	–40°C to +85°C	TSSOP-14	RU-14
AD7376AN1M	1,000	–40°C to +85°C	PDIP-14	N-14
AD7376AR1M	1,000	–40°C to +85°C	SOL-16	R-16
AD7376ARU1M	1,000	–40°C to +85°C	TSSOP-14	RU-14
Die Size: 101.6 mil	× 127.6 mil,	2.58 mm × 3.24 mm
Number Transistors: 840

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7376 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD7376–Typical Performance Characteristics

		100				0.5
	AB					0.4
OFPERCENTNOMINAL	%R				ERRORINL-R – LSB	0.3	TA = –558C
	RESISTANCEEND-TO- –						VB = 0V
		75				0.2	TA = +258C
						0.1	TA = +858C
		50				0
						–0.1	VDD = +15V
						–0.2	VSS = –15V
		25					VA = 2.5V
						–0.3
	END						RAB = 50kV
			RWB	RWA		–0.4

0							–0.5
0		32	64	96	128		0		16	32	48	64	80	96	112	128
			CODE – Decimal								CODE – Decimal

	0.25
	0.20
LSB	0.15						TA = –558C
	0.10	TA = +258C
–	0.05
ERROR
	0
	–0.05
DNL					TA = +858C
	–0.10
-
R
	–0.15						VDD = +15V
							VSS = –15V
	–0.20
							RAB = 50kV
	–0.25	16	32	48	64	80	96	112	128
	0

CODE – Decimal

Figure 2. Wiper To End Terminal	Figure 3. Resistance Step Position
Percent Resistance vs. Code	Nonlinearity Error vs. Code

Figure 4. Relative Resistance Step Change from Ideal vs. Code

NOMINAL END-TO-END RESISTANCE – kV

50

49VDD = +15V VSS = –15V

RAB = 50kV NOMINAL

48

47

46

45 –55 –35–15 5 25 45 65 85 105125

TEMPERATURE –8C

	14	01H
	12			10H
				20H
	10			40H
– V
	8
WA						TA = +258C
V	6					VDD = +15V
	4					VSS = –15V
			CODE = 70H			RAB = 50kV
	2						7FH
	0
	0	0.25	0.5	0.75	1	1.25	1.5	1.75	2
				IWA – mA

	1.5
			Iw = 100mA, TA = +258C
	1.2		DATA = 40H
LSB	0.9
R INL –
	0.6
	0.3
	0
	5	10	15	20	25	30
		SUPPLY VOLTAGE (VDD - VSS) – Volts

	Figure 5. Nominal Resistance vs.	Figure 6. Resistance Linearity vs.	Figure 7. Resistance Nonlinearity
		Conduction Current	Error vs. Supply Voltage
	Temperature

INL – LSB

1.0

0.8

0.6

0.4

0.2

0

							20										1000
				VA = 2.5V			15									–V	900	RAB = 50kV
				VB = 0V		TEMPCOMODE– ppm/8C	10									CONTACTWIPERRESISTANCE	800
					DV		–25				RAB = 50kV						100					VDD = +15V
				CODE = 40H	POTENTIOMETER		5										700
				RAB = 50kV																VDD = +5V
							0										600			VSS = 0V
							–5				VDD = +15V						500
							–10										400
					DT						VSS = –15V
																		VDD = +5V
							–15				VA = +2.5V						300
					/
					WB						VB = 0V						200	VSS = –5V
							–20
											–558C < TA < +858C
							–30										0					VSS = –15V
5	10	15	20	25	30		0	16	32	48	64	80	96	112	128		–55 –35–15		5	25	45	65	85	105	125
										CODE – Decimal								TEMPERATURE –8C
	SUPPLY VOLTAGE (VDD - VSS) – Volts

Figure 8. Potentiometer Divider	Figure 9. VWB/ T Potentiometer	Figure 10. Wiper Contact
Nonlinearity Error vs. Supply	Mode Tempco	Resistance vs. Temperature
Voltage

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