Analog Devices AD7537SE, AD7537LP, AD7537LN, AD7537KP, AD7537KN Datasheet

a		LC2MOS
		(8+4) Loading Dual 12-Bit DAC
		AD7537

FEATURES

Two 12-Bit DACs in One Package

DAC Ladder Resistance Matching: 0.5%

Space Saving Skinny DIP and Surface Mount Packages 4-Quadrant Multiplication

Low Gain Error (1 LSB max Over Temperature) Byte Loading Structure

Fast Interface Timing

APPLICATIONS

Automatic Test Equipment

Programmable Filters

Audio Applications

Synchro Applications

Process Control

GENERAL DESCRIPTION

The AD7537 contains two 12-bit current output DACs on one monolithic chip. A separate reference input is provided for each DAC. The dual DAC saves valuable board space, and the monolithic construction ensures excellent thermal tracking. Both DACs are guaranteed 12-bit monotonic over the full temperature range.

The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure. It is designed for right-justified data format. The control signals for register loading are A0, A1, CS, WR and UPD. Data is loaded to the input registers when CS and WR are low. To transfer this data to the DAC registers, UPD must be taken low with WR.

Added features on the AD7537 include an asynchronous CLR line which is very useful in calibration routines. When this is taken low, all registers are cleared. The double buffering of the data inputs allows simultaneous update of both DACs. Also, each DAC has a separate AGND line. This increases the device versatility; for instance one DAC may be operated with AGND biased while the other is connected in the standard configuration.

The AD7537 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL, 74HC and 5 V CMOS logic level inputs.

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FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1.DAC to DAC Matching:

Since both DACs are fabricated on the same chip, precise matching and tracking is inherent. Many applications which are not practical using two discrete DACs are now possible. Typical matching: 0.5%.

2.Small Package Size:

The AD7537 is packaged in small 24-pin 0.3" DIPs and in 28-terminal surface mount packages.

3.Wide Power Supply Tolerance:

The device operates on a +12 V to +15 V VDD, with ±10% tolerance on this nominal figure. All specifications are guaranteed over this range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] Fax: [phone]

AD7537–SPECIFICATIONS				(VDD = +12 V to +15 V, 610%, VREFA = VREFB = 10 V; IOUTA = AGND = 0 V,
				IOUTB = AGNDB = 0 V. All specifications TMIN to TMAX unless otherwise noted.)
	J, A	K, B		L, C	S	T	U
Parameter	Versions	Versions		Versions	Version	Version	Version	Units	Test Conditions/Comments
ACCURACY
Resolution	12	12		12	12	12	12	Bits
Relative Accuracy	± 1	± 1/2		± 1/2	± 1	± 1/2	± 1/2	LSB max
Differential Nonlinearity	± 1	± 1		± 1	± 1	± 1	± 1	LSB max	All grades guaranteed mono-
	± 6	± 3		± 1	± 6	± 3	± 2		tonic over temperature.
Gain Error								LSB max	Measured using RFBA, RFBB.
									Both DAC registers loaded
Gain Temperature Coefficient2;									with all 1s.
DGain/DTemperature	± 5	± 5		± 5	± 5	± 5	± 5	ppm/°C max	Typical value is 1 ppm/°C
Output Leakage Current
IOUTA
+25°C	10	10		10	10	10	10	nA max	DAC A Register loaded
TMIN to TMAX	150	150		150	250	250	250	nA max	with all 0s
IOUTB
+25°C	10	10		10	10	10	10	nA max	DAC B Register loaded
TMIN to TMAX	150	150		150	250	250	250	nA max	with all 0s
REFERENCE INPUT								kW min	Typical Input Resistance = 14 kW
Input Resistance	9	9		9	9	9	9
VREFA, VREFB	20	20		20	20	20	20	kW max
	± 3	± 3		± 1	± 3	± 3	± 1		Typically ±0.5%
Input Resistance Match								% max
DIGITAL INPUTS
VIH (lnput High Voltage)	2.4	2.4		2.4	2.4	2.4	2.4	V min
VIIL (Input Low Voltage)	0.8	0.8		0.8	0.8	0.8	0.8	V max
IIN (Input Current)
+25°C	± 1	± 1		± 1	± 1	± 1	± 1	mA max	VIN = VDD
TMIN to TMAX	± 10	± 10		± 10	± 10	± 10	± 10	mA max
CIN (lnput Capacitance)2	10	10		10	10	10	10	pF max
POWER SUPPLY3
VDD	10.8/16.5	10.8/16.5		10.8/16.5	10.8/16.5	10.8/16.5	10.8/16.5	V min/V max
IDD	2	2		2	2	2	2	mA max

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for Design Guidance only and are not subject to test.

(VDD = +12 V to +15 V; VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)

Parameter	TA = +258C	TA = TMIN, TMAX	Units			Test Conditions/Comments
Output Current Settling Time	1.5		ms max			To 0.01% of full-scale range. IOUT load = 100 W, CEXT = 13 pF.
						DAC output measured from falling edge of WR.
						Typical Value of Settling Time is 0.8 ms.
Digital-to-Analog Glitch lmpulse	7		nV-s typ			Measured with VREFA = VREFB = 0 V. IOUTA, IOUTB load = 100 W,
						CEXT = 13 pF. DAC registers alternately loaded with all 0s and all 1s.
AC Feedthrough4
VREFA to IOUTA	–70	–65	dB max			VREFA, VREFB = 20 V p-p 10 kHz sine wave.
VREFB to IOUTB	–70	–65	dB max			DAC registers loaded with all 0s.
Power Supply Rejection
DGain/DVDD	± 0.01	± 0.02	% per % max			DVDD = VDD max – VDD min
Output Capacitance
COUTA	70	70	pF max			DAC A, DAC B loaded with all 0s
COUTB	70	70	pF max
COUTA	140	140	pF max			DAC A, DAC B loaded with all 1s
COUTB	140	140	pF max
Channel-to-Channel Isolation
VREFA to IOUTB	–84		dB typ			VREFA = 20 V p-p 10 kHz sine wave, VREFB = 0 V.
						Both DACs loaded with all 1s.
VREFB to IOUTA	–84		dB typ			VREFB = 20 V p-p 10 kHz sine wave, VREFA = 0 V.
						Both DACs loaded with all 1s.
Digital Crosstalk	7		nV-s typ			Measured for a Code Transition of all 0s to all 1s.
						IOUTA, IOUTB load = 100 W, CEXT = 13 pF.
Output Noise Voltage Density	25		nV/Ö		typ	Measured between RFBA and IOUTA or RFBB and IOUTB.
				Hz
(10 Hz–100 kHz)						Frequency of measurement is 10 Hz–100 kHz.
Total Harmonic Distortion	–82		dB typ			VIN = 6 V rms, 1 kHz. Both DACs loaded with all 1s.

NOTES

1Temperature range as follows: J, K, L Versions: –40°C to +85°C; A, B, C Versions: –40°C to +85°C; S, T, U Versions: –55°C to +125°C

Specifications subject to change without notice.

2Sample tested at +25°C to ensure compliance. 3Functional at VDD = 5 V, with degraded specifications. 4Pin 12 (DGND) on ceramic DIPs is connected to lid.

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AD7537

TIMING CHARACTERISTICS (VDD = +10.8 V to +16.5 V, VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V.)

		Limit at	Limit at
	Limit at	TA = –408C	TA = +558C
Parameter	TA = +258C	to +858C	to +1258C	Units	Test Conditions/Comments
t1	15	15	30	ns min	Address Valid to Write Setup Time
t2	15	15	25	ns min	Address Valid to Write Hold Time
t3	60	80	80	ns min	Data Setup Time
t4	25	25	25	ns min	Data Hold Time
t5	0	0	0	ns min	Chip Select or Update to Write Setup Time
t6	0	0	0	ns min	Chip Select or Update to Write Hold Time
t7	80	80	100	ns min	Write Pulse Width
t8	80	80	100	ns min	Clear Pulse Width

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise stated)

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VREFA, VREFB to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V VRFBA, VRFBB to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V

IOUTA, IOUTB to DGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, VDD +0.3 V Power Dissipation (Any Package)

To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature Range

Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C Extended Hermetic (S, T, U Versions) . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7537 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

		ORDERING GUIDE1
		Temperature	Relative	Gain	Package
	Model2	Range	Accuracy	Error	Option3
	AD7537JN	–40°C to +85°C	±1 LSB	±6 LSB	N-24
	AD7537KN	–40°C to +85°C	±1/2 LSB	±3 LSB	N-24
	AD7537LN	–40°C to +85°C	±1/2 LSB	±1 LSB	N-24
	AD7537JP	–40°C to +85°C	±1 LSB	±6 LSB	P-28A
	AD7537KP	–40°C to +85°C	±1/2 LSB	±3 LSB	P-28A
	AD7537LP	–40°C to +85°C	±1/2 LSB	±1 LSB	P-28A
	AD7537AQ	–40°C to +85°C	±1 LSB	±6 LSB	Q-24
	AD7537BQ	–40°C to +85°C	±1/2 LSB	±3 LSB	Q-24
	AD7537CQ	–40°C to +85°C	±1/2 LSB	±1 LSB	Q-24
Figure 1. Timing Diagram	AD7537SQ	–55°C to +125°C	±1 LSB	±6 LSB	Q-24
	AD7537TQ	–55°C to +125°C	±1/2 LSB	±3 LSB	Q-24
	AD7537UQ	–55°C to +125°C	±1/2 LSB	±2 LSB	Q-24
	AD7537SE	–55°C to +125°C	±1 LSB	±6 LSB	E-28A
	AD7537TE	–55°C to +125°C	±1/2 LSB	±3 LSB	E-28A
	AD7537UE	–55°C to +125°C	±1/2 LSB	±2 LSB	E-28A

NOTES

1Analog Devices reserves the right to ship ceramic packages (D-24A) in lieu of cerdip packages (Q-24).

2To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet.

3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.

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