Analog Devices AD8174AR-REEL, AD8174AR, AD8174AN, AD8170AR-REEL, AD8170AR Datasheet

a	250 MHz, 10 ns Switching
	Multiplexers w/Amplifier

FEATURES

Fully Buffered Inputs and Outputs Fast Channel Switching: 10 ns

Internal Current Feedback Output Amplifier High Output Drive: 50 mA

Flexible Gain Setting via External Resistor(s) High Speed

250 MHz Bandwidth, G = +2

1000 V/ms Slew Rate

Fast Settling Time of 15 ns to 0.1% Low Power: < 10 mA

Excellent Video Specifications (RL = 150 V, G = +2)

Gain Flatness of 0.1 dB Beyond 80 MHz 0.02% Differential Gain Error

0.058 Differential Phase Error

Low Crosstalk of –78 dB @ 5 MHz

High Disable Isolation of –88 dB @ 5 MHz High Shutdown Isolation of –92 dB @ 5 MHz Low Cost

Fast Output Disable Feature for Connecting Multiple Devices (AD8174 Only)

Shutdown Feature Reduces Power to 1.5 mA (AD8174 Only)

APPLICATIONS

Pixel Switching for “Picture-In-Picture”

LCD and Plasma Displays

Video Routers

PRODUCT DESCRIPTION

The AD8170(2:1) and AD8174(4:1) are very high speed buffered multiplexers. These multiplexers offer an internal current feedback output amplifier whose gain can be programmed via external resistors and is capable of delivering 50 mA of output current. They offer –3 dB signal bandwidth of 250 MHz and slew rate of greater than 1000 V/μs. Additionally, the AD8170 and AD8174 have excellent video specifications with low differential gain and differential phase error of 0.02% and 0.05° and 0.1 dB flatness out to 80 MHz. With a low 78 dB of crosstalk and better than 88 dB isolation, these devices are useful in many high speed applications. These are low power devices consuming only 9.7 mA from a ±5 V supply.

AD8170/AD8174

FUNCTIONAL BLOCK DIAGRAM

		LOGIC	AD8170
SELECT	1			8	VOUT
GND	2			7	–VIN
–VS	3			6	+VS
IN0	4	+1	+1	5	IN1
			AD8174
IN0	1	+1		14	+VS
GND	2			13	VOUT
IN1	3	+1		12	–VIN
GND	4	2		11	SD
IN2	5	+1	LOGIC	10	ENABLE
–VS	6			9	A1
IN3	7	+1	2	8	A0

The AD8174 offers a high speed disable feature allowing the output to be put into a high impedance state for cascading stages so that the off channels do not load the output bus. Additionally, the AD8174 can be shut down (SD) when not in use to minimize power consumption (IS = 1.5 mA). These products will be offered in 8-lead and 14-lead PDIP and SOIC packages.

0

VIN = 50mV rms

–1

G = +2

RF = 499Ω (AD8170R)

–2

– dB

RF = 549Ω (AD8174R)

FLATNESSNORMALIZED– dB

0.1

RL = 100Ω

–3

NORMALIZEDOUTPUT

0

–4

–0.1

–5

–0.2

–6

–0.3

–7

–0.4

–8

–0.5

–9

1M

10M

100M

1G

FREQUENCY – Hz

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1. Small Signal Frequency Response

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(@ TA = +258C, VS = 65 V, RL = 150 V, G = +2, RF = 499 V

AD8170/AD8174–SPECIFICATIONS (AD8170R), RF = 549 V (AD8174R) unless otherwise noted)

AD8170A/AD8174A

Parameter

Conditions

Min

Typ

Max

Units

SWITCHING CHARACTERISTICS

Switching Time1

Channel-to-Channel

50% Logic to 10% Output Settling

IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V

7.5

ns

50% Logic to 90% Output Settling

IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V

9.1

ns

50% Logic to 99.9% Output Settling

IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V

25

ns

ENABLE

to Channel ON Time2 (AD8174R)

50% Logic to 90% Output Settling

IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V

17

ns

ENABLE

to Channel OFF Time2 (AD8174R)

50% Logic to 90% Output Settling

IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V

120

ns

Shutdown to Channel ON Time3 (AD8174R)

50% Logic to 90% Output Settling

IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V

20

ns

Shutdown to Channel OFF Time3 (AD8174R)

50% Logic to 90% Output Settling

IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V

115

ns

Channel Switching Transient (Glitch)4

All Inputs Grounded

138 /104

mV p-p

DIGITAL INPUTS

Logic “1” Voltage

SELECT, A0, A1,

ENABLE

, SD Inputs, TMIN–TMAX

2.0

V

Logic “0” Voltage

SELECT, A0, A1,

ENABLE

, SD Inputs, TMIN–TMAX

0.8

V

Logic “1” Input Current

SELECT, A0, A1 Inputs, TMIN–TMAX

50

300

nA

ENABLE

, SD Inputs, TMIN–TMAX

1

5

mA

Logic “0” Input Current

SELECT, A0, A1 Inputs, TMIN–TMAX

3

5

mA

ENABLE

, SD Inputs, TMIN–TMAX

30

300

nA

DYNAMIC PERFORMANCE

VO = 50 mV rms, RL = 100 W

–3 dB Bandwidth (Small Signal)5

250

MHz

–3 dB Bandwidth (Large Signal)5

VO = 1 V rms, RL = 100 W

100

MHz

0.1 dB Bandwidth5

VO = 50 mV rms, RF = 499 W (AD8170R), RL = 100 W

VO = 50 mV rms, RF = 549 W (AD8174R), RL = 100 W

85

MHz

Rise and Fall Time (10% to 90%)

2 V Step

1.6

ns

Slew Rate

2 V Step

1000

V/ms

Settling Time to 0.1%

2 V Step

15

ns

DISTORTION/NOISE PERFORMANCE

Differential Gain

ƒ = 3.58 MHz

0.02

%

Differential Phase

ƒ = 3.58 MHz

0.05

Degrees

All Hostile Crosstalk6

AD8170R

ƒ = 5 MHz, RL = 100 W

–80

dB

ƒ = 30 MHz, RL = 100 W

–65

dB

AD8174R

ƒ = 5 MHz, RL = 100 W

–78

dB

ƒ = 30 MHz, RL = 100 W

–63

dB

Disable Isolation7

AD8174R

ƒ = 5 MHz, RL = 100 W

–88

dB

ƒ = 30 MHz, RL = 100 W

–72

dB

Shutdown Isolation8

AD8174R

ƒ = 5 MHz, RL = 100 W

–92

dB

ƒ = 30 MHz, RL = 100 W

–77

dB

Input Voltage Noise

ƒ = 10 kHz to 30 MHz

10

nV/Ö

Hz

+Input Current Noise

ƒ = 10 kHz to 30 MHz

1.6

pA/Ö

Hz

–Input Current Noise

ƒ = 10 kHz to 30 MHz

8.5

pA/Ö

Hz

Total Harmonic Distortion

ƒC = 10 MHz, VO = 2 V p-p, RL = 150 W

–60

dBc

ƒC = 10 MHz, VO = 2 V p-p, RL = 1 kW

–72

dBc

DC/TRANSFER CHARACTERISTICS

kW

Transresistance

400

600

Open-Loop Voltage Gain

G = +1, RF = 1 kW

2000

6000

V/V

Gain Accuracy9

0.4

%

Gain Matching

Channel-to-Channel

0.05

%

Input Offset Voltage

5

9

mV

TMIN to TMAX

12

mV

Input Offset Voltage Matching

Channel-to-Channel

1.5

5

mV

Input Offset Voltage Drift

11

mV/°C

Input Bias Current

(+) Switch Input

7

15

mA

TMIN to TMAX

15

mA

(–) Buffer Input

3

10

mA

TMIN to TMAX

14

mA

Input Bias Current Drift

(+) Switch and (–) Buffer Input

20

nA/°C

–2–

REV. 0

AD8170/AD8174

				AD8170A/AD8174A
Parameter		Conditions		Min	Typ	Max	Units
INPUT CHARACTERISTICS							MΩ
Input Resistance		(+) Switch Input			1.7
		(–) Buffer Input			100		Ω
Input Capacitance		Channel Enabled (R Package)			1.1		pF
		Channel Disabled (R Package)			1.1		pF
Input Voltage Range					±3.3		V
Input Common-Mode Rejection Ratio		+CMRR,	VCM = 1 V	51	56		dB
		–CMRR,	VCM = 1 V	50	52		dB
OUTPUT CHARACTERISTICS		RL = 1 kΩ, TMIN–TMAX		±4.0	±4.26
Output Voltage Swing							V
		RL = 150 Ω, TMIN–TMAX		±3.5	±4.0		V
Output Current		RL = 10 Ω			50		mA
Short Circuit Current					180		mA
Output Resistance		Enabled			10		mΩ
		Disabled (AD8174)			10		MΩ
Output Capacitance		Disabled (AD8174)			7.5		pF
POWER SUPPLY				±4		±6
Operating Range							V
Power Supply Rejection Ratio	+PSRR	+VS = +4.5 V to +5.5 V, –VS = –5 V		58	66		dB
		TMIN–TMAX		55			dB
	–PSRR	–VS = –4.5 V to –5.5 V, +VS= +5 V		52	58		dB
		TMIN–TMAX		50			dB
Quiescent Current		All Channels “ON”, TMIN–TMAX			8.7/9.7	11/13	mA
		AD8174 Disabled, TMIN–TMAX			4.1	5	mA
		AD8174 Shutdown, TMIN–TMAX			1.5	2.5	mA
OPERATING TEMPERATURE RANGE				–40		+85	°C

NOTES

1Shutdown (SD) and ENABLE pins are grounded (AD8174). IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. Measure transition time from 50% of SELECT (A0 or A1) input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 (or IN2) channel voltage (+0.5 V) to IN1 (or IN3 = –0.5 V) or vice versa.

2AD8174 only. Shutdown (SD) pin is grounded. ENABLE pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines which channel is activated (i.e., if A0 = Logic 0 and A1 = Logic 1, then IN2 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-

sure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, tOFF is the disable time, tON is the enable time. 3AD8174 only. ENABLE pin is grounded. Shutdown (SD) pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines which channel is activated (i.e., if A0 = Logic 1 and A1 = Logic O, then IN1 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and measure transition time from 50% of SD pulse (+2.5 V) to 90% of the total output voltage change. In Figure 6, tOFF is the shutdown assert time, tON is the shutdown release time.

4All inputs are grounded. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT (A0 or A1) pulse increases the glitch magnitude due to coupling via the ground plane.

5Bandwidth of the multiplexer is dependent upon the resistor feedback network. Refer to Table III for recommended feedback component values, which give the best compromise between a wide and a flat frequency response.

6Select input(s) that is (are) not being driven (i.e., if SELECT is Logic 1, activated input is IN1; in AD8174, if A0 = Logic 0, A1 = Logic 1, activated input is IN2). Drive all other inputs with VIN = 0.707 V rms, and monitor output at f = 5 MHz and 30 MHz; RL = 100 Ω (see Figure 13).

7AD8174 only. Shutdown (SD) pin is grounded. Mux is disabled, (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with VIN = 0.354 V rms. Output is monitored at f = 5 MHz and 30 MHz; RL = 100 Ω. In this mode, the output impedance of the disabled mux is very high (typ 10 M Ω), and the signal couples across the package; the load impedance and the feedback network determine the crosstalk. For instance, in a closed-loop gain of +1, r OUT ˘ 10 MΩ, in a gain of +2 (RF = RG = 549 Ω), rOUT = 1.1 kΩ (see Figure 14).

8AD8174 only. ENABLE pin is grounded. Mux is shutdown (i.e., SD = Logic 1), and all inputs are driven simultaneously with V IN = 0.354 V rms. Output is monitored at f = 5 MHz and 30 MHz; RL = 100 Ω. (see Figure 14). The mux output impedance in shutdown mode is the same as the disabled mux output impedance. 9For Gain Accuracy expression, refer to Equation 4.

Specifications subject to change without notice.

Table I. AD8170 Truth Table Table II. AD8174 Truth Table

SELECT VOUT

0IN0

1IN1

A0	A1				SD	VOUT
			ENABLE
0	0	0			0	IN0
1	0	0			0	IN1
0	1	0			0	IN2
1	1	0			0	IN3
X	X	1			0	HIGH Z, IS = 4.1 mA
X	X		X		1	HIGH Z, IS = 1.5 mA

REV. 0

–3–

AD8170/AD8174

ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . .12.6 V
Internal Power Dissipation2
AD8170 8-Lead Plastic (N) . . . . . . . . . . . .	. . . . . 1.3 Watts
AD8170 8-Lead Small Outline (R) . . . . . .	. . . . . 0.9 Watts
AD8174 14-Lead Plastic (N) . . . . . . . . . . .	. . . . . 1.6 Watts
AD8174 14-Lead Small Outline (R) . . . . .	. . . . . 1.0 Watts
Input Voltage (Common Mode) . . . . . . . . . .	. . . . . . . . . . ±VS
Output Short Circuit Duration . . Observe Power Derating Curves
Storage Temperature Range	–65°C to +125°C
N & R Packages . . . . . . . . . . . . . . . . . . . .
Lead Temperature Range (Soldering 10 sec) .	. . . . . . . +300°C

NOTES

1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Specification is for device in free air: 8-Pin Plastic Package: θJA = 90°C/Watt; 8-Pin SOIC Package: θJA = 160°C/Watt; 14-Pin Plastic Package: θJA = 90°C/Watt 14-Pin SOIC Package: θJA = 120°C/Watt, where PD = (TJ–TA)/θJA.

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Option
AD8170AN	–40°C to +85°C	8-Pin Plastic DIP	N-8
AD8170AR	–40°C to +85°C	8-Pin SOIC	SO-8
AD8170AR-REEL	–40°C to +85°C	Reel 8-Pin SOIC	SO-8
AD8174AN	–40°C to +85°C	14-Pin Plastic DIP	N-14
AD8174AR	–40°C to +85°C	14-Pin Narrow SOIC	R-14
AD8174AR-REEL	–40°C to +85°C	Reel 14-Pin SOIC	R-14
AD8170-EB	Evaluation Board	For AD8170R
AD8174-EB	Evaluation Board	For AD8174R

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8170 and AD8174 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure.

While the AD8170 and AD8174 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figures 2 and 3.

	2.0
– Watts	8-PIN MINI-DIP PACKAGE							TJ = +150°C
DISSIPATION	1.5
	1.0
POWER
MAXIMUM	8-PIN SOIC PACKAGE
	0.5
	0	0	10	20	30	40	50	60	70	80	90
	–50 –40 –30 –20 –10
	AMBIENT TEMPERATURE – °C

Figure 2. AD8170 Maximum Power Dissipation vs.

Temperature
	2.5
– Watts										TJ = +150°C
	2.0
DISSIPATION
							14-PIN DIP PACKAGE
	1.5
POWER
		14-PIN SOIC
MAXIMUM
	1.0
	0.5	–40 –30 –20	–10	0	10	20	30	40	50	60	70	80	90
	–50
			AMBIENT TEMPERATURE – °C

Figure 3. AD8174 Maximum Power Dissipation vs. Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8170/AD8174 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

Typical Performance Characteristics – AD8170/AD8174

		tFALL = 9.1ns	tRISE = 7.5ns
	DUT	OUTPUT
	OUT
500mV/DIV		IN0, IN2 =		G = +2
			+0.5V
				RF = RG = 499V
		IN1, IN3 =
			+0.5V	RL = 100V
				SELECT
				PULSE
				0 TO +5V
			5ns/DIV

Figure 4. Channel Switching Characteristics

				AD8174R			INØ = +0.5VDC
							G = +2
							RF = 549V
				OUTPUT
							RL = 100V
	200mV/DIV
							tOFF = 120ns
				tON		= 17ns	ENABLE PULSE
							0 TO +5V
							(5nsec EDGES)
						50ns/DIV

Figure 5. Enable and Disable Switching Characteristics

	OUTPUT	AD8174R
		INØ = +0.5VDC
		G = +2
		RF = 549V
200mV/DIV		RL = 100V
	tON = 20ns
		tOFF = 115ns
		SHUTDOWN PULSE
		0 TO +5V
		(5nsec EDGES)
		50ns/DIV

Figure 6. Shutdown Switching Characteristics

OUTPUT (AD8170R) SEL SWITCHING

	G = +2	RF = 549V
	RF = 499V	(AD8174R)
	(AD8170R)	RL = 100V
50mV/DIV	OUTPUT	A0 SWITCHING
	(AD8174R)
		A1 SWITCHING
		SEL, A0, A1
		PULSE
		0 TO +5V

10ns/DIV

Figure 7. Switching Transient (Glitch) Response

	4
	3	G = +2
		RF = RG = 1kΩ
		RL = 150Ω
	2
– Volts	1
	0
OUT
V	–1
	–2
	–3
	–4	–2	–1	0	1	2	3
	–3
				VIN – Volts

Figure 8. Output Voltage vs. Input Voltage, G = +2

	9				9
	6	VIN = 1.0V rms		G = +2	0
				RF = 549Ω
	3			RL = 100Ω	–3
– dBV	0	VIN = 0.5V rms			–6
						dBV
	–3				–9
OUTPUT LEVEL						INPUT LEVEL –
	–6	VIN = 0.25V rms			–12
	–9				–15
	–12	VIN = 125mV rms			–18
	–15				–21
	–18	VIN = 625mV rms			–24
	–21				–27
	1M	10M	100M		1G

FREQUENCY – Hz

Figure 9. Large Signal Frequency Response

REV. 0

–5–