Texas Instruments JM38510-10404BEA, SN55115J, SN75115D, SN75115DR, SN75115N Datasheet

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SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS

SLLS072D ± SEPTEMBER 1973 ± REVISED MAY 1998

DChoice of Open-Collector or Active Pullup (Totem-Pole) Outputs

DSingle 5-V Supply

DDifferential Line Operation

DDual-Channel Operation

DTTL Compatible

D± 15-V Common-Mode Input Voltage Range

DOptional-Use Built-In 130-Ω Line-

Terminating Resistor

DIndividual Frequency-Response Controls

DIndividual Channel Strobes

DDesigned for Use With SN55113, SN75113, SN55114, and SN75114 Drivers

SN55115 . . . J OR W PACKAGE SN75115 . . . N PACKAGE (TOP VIEW)

1YS

 

1

16

 

VCC

 

 

 

 

 

 

1YP

 

2

15

 

2YS

1STRB

 

3

14

 

2YP

 

 

1RTC

 

4

13

 

2STRB

 

 

1B

 

5

12

 

2RTC

 

 

1RT

 

6

11

 

2B

 

 

 

 

10

 

1A

 

7

 

2RT

 

 

9

 

GND

 

8

 

2A

 

 

 

 

 

 

SN55114 . . . FK PACKAGE

(TOP VIEW)

DDesigned to Be Interchangeable With National DS9615 Line Receivers

description

The SN55115 and SN75115 dual differential line receivers are designed to sense small differential signals in the presence of large common-mode noise. These devices give TTL-compatible output signals as a function of the differential input voltage. The open-collector output configuration permits the wire-ANDing of similar TTL outputs (such as SN5401/SN7401) or other SN55115/SN75115 line receivers. This permits a level of logic to be implemented without extra delay.

 

1YP

1YS

NC

CC

2YS

 

 

V

 

1STRB

3

2

1

20 19

2YP

4

 

 

 

18

1RTC

5

 

 

 

17

2STRB

NC

6

 

 

 

16

NC

1B

7

 

 

 

15

2RTC

1RT

8

 

 

 

14

2B

 

9

10 11 12 13

 

 

1A

GND

NC

2A

T

 

 

2R

 

NC ± No internal connection

The output stages are similar to TTL totem-pole outputs, but with sink outputs, 1YS and 2YS, and the corresponding active pullup terminals, 1YP and 2YP, available on adjacent package pins. The frequency response and noise immunity may be provided by a single external capacitor. A strobe input is provided for each channel. With the strobe in the low level, the receiver is disabled and the outputs are forced to a high level.

The SN55115 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN75115 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

 

 

OUTPUT

STRB

DIFF INPUT

(YP AND YS

(A AND B)

TIED

 

 

 

TOGETHER)

 

 

 

L

X

H

H

L

H

H

H

L

 

 

 

H = VI VIH min or VID more positive than VT + max

L = VI VIL max or VID more negative thanVT ± max

X = irrelevant

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

1

SN55115, SN75115

DUAL DIFFERENTIAL RECEIVERS

SLLS072D ± SEPTEMBER 1973 ± REVISED MAY 1998

logic symbol²

5

&

1B

2

7

1A

1YP

6

 

1RT

RT

3

1

1STRB

1YS

4

RSP

1RTC

11

 

2B

14

9

2A

2YP

10

 

2RT

15

13

2STRB

2YS

12

 

2RTC

 

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

 

5

 

1B

2

1YP (Pullup)

 

7

 

1A

1

1YS (Sink)

1RT

6

 

4

 

1RTC

3

 

1STRB

 

 

 

 

11

 

2B

14

2YP (Pullup)

 

9

 

2A

15

2YS (Sink)

2RT

10

 

12

 

2RTC

 

 

13

2STRB

2

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Texas Instruments JM38510-10404BEA, SN55115J, SN75115D, SN75115DR, SN75115N Datasheet

SN55115, SN75115

DUAL DIFFERENTIAL RECEIVERS

 

 

 

 

 

 

 

SLLS072D ± SEPTEMBER 1973 ± REVISED MAY 1998

schematic (each receiver)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Response

 

 

 

 

 

 

RT

 

Strobe

Time

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

6,10

3,13

4,12

 

16

 

1 k

1 k

V

 

2.7 k

V

 

2 k

VCC

 

 

 

V

 

 

 

 

 

 

 

 

 

1.5 k

1.64 k

1.64 k

130

2.6 k

2.6 k

 

 

 

 

 

 

 

 

 

 

1 pF

 

 

1 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input 7.9

 

 

 

500

500

 

 

 

20

A

 

 

 

 

 

 

 

 

2,14 Pullup

 

 

 

 

 

 

 

 

YP

8 k

 

 

8 k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7 k

 

 

 

 

 

5 k

7 k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input 5.11

 

 

 

 

 

 

3 k

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

 

 

 

 

 

1,15 Sink

130

150

 

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

YS

 

 

150

 

 

150

 

1.5 k

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

Common to

 

 

 

 

 

 

 

 

Both Receivers

 

 

 

 

 

 

 

2.5 k

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

150

Resistor values are nominal and in ohms.

Pin numbers shown are for the J, N, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . 7

V

Input voltage VI (A, B, and RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . ±25

V

Input voltage VI (STRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . 5.5

V

Off-state voltage applied to open-collector outputs . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . 14

V

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

See Dissipation Rating Table

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . .

±65°C to 150°C

Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package . . . . . . . . .

. . . . . . . 300°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . .

. . . . . . . . . . . .

. . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential input voltage, are with respect to network ground terminal.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

3

SN55115, SN75115

DUAL DIFFERENTIAL RECEIVERS

SLLS072D ± SEPTEMBER 1973 ± REVISED MAY 1998

DISSIPATION RATING TABLE

PACKAGE

TA 25°C

DERATING FACTOR

TA = 70°C

TA = 125°C

POWER RATING

ABOVE TA = 25°C

POWER RATING

POWER RATING

 

FK²

1375 mW

11.0 mW/°C

880 mW

275 mW

J²

1375 mW

11.0 mW/°C

880 mW

275 mW

N

1150 mW

9.2 mW/°C

736 mW

Ð

W²

1000 mW

8.0 mW/°C

640 mW

200 mW

²In the FK, J, and W packages, SN55115 chips are either silver glass or alloy mounted. SN75115 chips are glass mounted.

recommended operating conditions

 

 

SN55115

 

 

SN75115

 

UNIT

 

 

 

 

 

 

 

 

MIN

NOM

MAX

MIN

NOM

MAX

 

 

 

 

 

 

 

 

 

 

Supply voltage, VCC

4.5

5

5.5

4.75

5

5.25

V

High-level input voltage at STRB, VIH

2.4

 

 

2.4

 

 

V

Low-level input voltage at STRB, VIL

 

 

0.4

 

 

0.4

V

High-level output current, IOH

 

 

± 5

 

 

± 5

mA

Low-level output current, IOL

 

 

15

 

 

15

mA

Operating free-air temperature, TA

± 55

 

125

0

 

70

°C

4

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