MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Binary Counter
The MC10H016 is a high±speed synchronous, presettable, cascadable 4±bit binary counter. It is useful for a large number of conversion, counting and digital integration applications.
•Counting Frequency, 200 MHz Minimum
•Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
•Voltage Compensated
•MECL 10K±Compatible
•Positive Edge Triggered
MAXIMUM RATINGS
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Characteristic |
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Symbol |
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Rating |
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Unit |
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Power Supply (VCC = 0) |
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VEE |
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±8.0 to 0 |
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Vdc |
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Input Voltage (VCC = 0) |
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VI |
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0 to VEE |
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Vdc |
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Output Current Ð Continuous |
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Iout |
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50 |
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mA |
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Ð Surge |
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100 |
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Operating Temperature Range |
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TA |
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0 to +75 |
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°C |
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Storage Temperature Range Ð Plastic |
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Tstg |
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±55 to +150 |
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°C |
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Ð Ceramic |
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±55 to +165 |
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ELECTRICAL CHARACTERISTICS (VEE = ±5.2 V ±5%) (See Note) |
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0° |
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25° |
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75° |
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Characteristic |
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Symbol |
Min |
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Max |
Min |
Max |
Min |
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Max |
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Unit |
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Power Supply Current |
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IE |
Ð |
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126 |
Ð |
115 |
Ð |
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126 |
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mA |
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Input Current High |
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IinH |
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μA |
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All Except MR |
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Ð |
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450 |
Ð |
265 |
Ð |
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265 |
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Pin 12 MR |
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Ð |
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1190 |
Ð |
700 |
Ð |
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700 |
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Input Current Low |
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IinL |
0.5 |
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Ð |
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0.5 |
Ð |
0.3 |
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Ð |
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μA |
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High Output Voltage |
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VOH |
±1.02 |
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±0.84 |
±0.98 |
±0.81 |
±0.92 |
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±0.735 |
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Vdc |
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Low Output Voltage |
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VOL |
±1.95 |
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±1.63 |
±1.95 |
±1.63 |
±1.95 |
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±1.60 |
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Vdc |
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High Input Voltage |
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VIH |
±1.17 |
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±0.84 |
±1.13 |
±0.81 |
±1.07 |
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±0.735 |
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Vdc |
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Low Input Voltage |
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VIL |
±1.95 |
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±1.48 |
±1.95 |
±1.48 |
±1.95 |
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±1.45 |
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Vdc |
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AC PARAMETERS |
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Propagation Delay |
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tpd |
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ns |
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Clock to Q |
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1.0 |
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2.4 |
1.0 |
2.5 |
1.0 |
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2.7 |
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Clock to TC |
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0.7 |
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2.4 |
0.7 |
2.5 |
0.7 |
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2.6 |
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MR to Q |
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0.7 |
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2.4 |
0.7 |
2.5 |
0.7 |
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2.6 |
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Set±up Time |
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tset |
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ns |
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Pn to Clock |
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2.0 |
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Ð |
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2.0 |
Ð |
2.0 |
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Ð |
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CE or PE to Clock |
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2.5 |
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Ð |
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2.5 |
Ð |
2.5 |
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Ð |
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Hold Time |
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thold |
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ns |
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Clock to Pn |
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1.0 |
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Ð |
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1.0 |
Ð |
1.0 |
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Ð |
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Clock to CE or PE |
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0.5 |
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Ð |
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0.5 |
Ð |
0.5 |
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Ð |
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Counting Frequency |
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fcount |
200 |
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Ð |
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200 |
Ð |
200 |
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Ð |
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MHz |
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Rise Time |
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tr |
0.5 |
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2.0 |
0.5 |
2.1 |
0.5 |
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2.2 |
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ns |
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Fall Time |
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tf |
0.5 |
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2.0 |
0.5 |
2.1 |
0.5 |
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2.2 |
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ns |
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NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50±ohm resistor to ±2.0 volts.
MC10H016
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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Q1 |
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2 |
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15 |
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Q2 |
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Q0 |
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3 |
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14 |
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Q3 |
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CP |
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TC |
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4 |
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13 |
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MR |
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PE |
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5 |
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12 |
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P3 |
CE |
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6 |
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11 |
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PO |
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7 |
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10 |
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P2 |
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VEE |
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8 |
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9 |
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P1 |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
TRUTH TABLE
CE |
PE |
MR |
CP |
Function |
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L |
L |
L |
Z |
Load Parallel (Pn to Qn) |
H |
L |
L |
Z |
Load Parallel (Pn to Qn) |
L |
H |
L |
Z |
Count |
H |
H |
L |
Z |
Hold |
X |
X |
L |
ZZ |
Masters Respond; |
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Slaves Hold |
X |
X |
H |
X |
Reset (Qn = LOW, |
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TC = HIGH) |
Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low)
Features include assertion inputs and outputs on each of the four master/slave counting flip±flops. Terminal count is generated internally in a manner that allows synchronous loading at nearly the speed of the basic counter.
9/96
Motorola, Inc. 1996 |
2±1 |
REV 6 |
MOTOROLA
2±2
Data MECL
6 Rev Ð DL122
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4±Bit Binary Counter Logic Diagram |
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PE |
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Q0 |
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Q1 |
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Q2 |
Q3 |
MASTER |
Q |
SLAVE |
P1 |
MASTER |
Q |
SLAVE |
P2 |
MASTER |
Q |
SLAVE |
P3 |
P0 |
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Q |
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Q |
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Q |
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MR |
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Q |
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Q |
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Q |
Q |
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CE |
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CP |
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TC |
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Note that this diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many gate functions are achieved internally without incurring a full gate delay.
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1/2 10H109 |
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Q0±Q3 |
Q0±Q3 |
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Q0±Q3 |
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Q0±Q3 |
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Q0±Q3 |
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FO |
CE |
PE |
CE |
PE |
CE |
PE |
CE |
PE |
CE |
PE |
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LSB |
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MSB |
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MR |
MR |
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MR |
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MR |
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MR |
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C |
Tc |
C |
Tc |
C |
Tc |
C |
Tc |
C |
Tc |
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P0±P3 |
P0±P3 |
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P0±P3 |
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P0±P3 |
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P0±P3 |
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1/2 10H109 |
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1/2 10H109 |
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1/2 10H109 |
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CLOCK 
N Counter 1 to 16 5
MC10H016 Cascaded for 5 Stage Presettable Counter
Max freq. is only OR gate delay below max when counting alone.
MC10H016
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