MC10H103FN
SEMICONDUCTOR TECHNICAL DATA
The MC10H103 is a quad 2–input OR gate. The MC10H103 provides one
gate with OR/NOR outputs. This MECL 10H part is a functional/pinout
duplication of the standard MECL 10K family part, with 100% improvement in
propagation delay, and no increases in power– supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 25 mW/Gate (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V
Input Voltage (VCC = 0) V
Output Current— Continuous
— Surge
Operating Temperature Range T
Storage Temperature Range— Plastic
— Ceramic
I
T
EE
I
out
A
stg
–8.0 to 0 Vdc
0 to V
EE
50
100
0 to +75 °C
–55 to +150
–55 to +165
Vdc
mA
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Current I
Input Current High I
Input Current Low I
High Output Voltage V
Low Output Voltage V
High Input Voltage V
Low Input Voltage V
E
inH
inL
OH
OL
IH
— 29 — 26 — 29 mA
— 425 — 265 — 265 µA
0.5 — 0.5 — 0.3 — µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
IL
AC PARAMETERS
Propagation Delay t
Rise Time t
Fall Time t
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
pd
0.4 1.3 0.4 1.3 0.45 1.45 ns
0.5 1.7 0.5 1.8 0.5 1.9 ns
r
0.5 1.7 0.5 1.8 0.5 1.9 ns
f
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
4
5
6
7
12
13
10
11
V
= PIN 1
CC1
V
= PIN 16
CC2
VEE = PIN 8
DIP
PIN ASSIGNMENT
V
A
OUT
B
OUT
CC1
A
IN
A
IN
B
IN
B
IN
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
C
OUT
D
OUT
C
IN
C
IN
D
IN
D
IN
C
OUT
2
3
15
9
14
3/93
Motorola, Inc. 1996
2–86
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
REV 5
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