Fairchild Semiconductor MM74HC574WMX, MM74HC574SJ, MM74HC574MTC, MM74HC574MTCX, MM74HC574WM Datasheet

September 1983

Revised February 1999

MM74HC574

3-STATE Octal D-Type Edge-Triggered Flip-Flop

General Description

The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system.

These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what

signals are present at the other inputs and the state of the storage elements.

The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

■Typical propagation delay: 18 ns

■Wide operating voltage range: 2V–6V

■Low input current: 1 μA maximum

■Low quiescent current: 80 μA maximum

■Compatible with bus-oriented systems

■Output drive capability: 15 LS-TTL loads

Ordering Code:

Order Number	Package Number	Package Description
MM74C574WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300”
MM74C574SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74C574MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4m Wide
MM74C574N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP		Output	Clock	Data	Output
		Control
		L	−	H	H
		L	−	L	L
		L	L	X	Q0
		H	X	X	Z

H = HIGH Level

L = LOW Level

X = Don't Care

− = Transition from LOW-to-HIGH Z = High Impedance State

Q0 = The level of the output before steady state input conditions were established

Top View

Flop-Flip Triggered-Edge Type-D Octal STATE-3 MM74HC574

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MM74HC574

DC Output Voltage (VOUT)

−0.5 to VCC +0.5V

DC Input or Output Voltage

0

VCC

V

Absolute Maximum Ratings(Note 1)

Recommended Operating

(Note 2)

Conditions

Supply Voltage (VCC)

−0.5 to +7.0V

Min

Max

Units

DC Input Voltage (VIN)

−1.5 to VCC +1.5V

Supply Voltage (V

CC

)

2

6

V

Clamp Diode Current (IIK, IOK)

±20 mA

(V

,V

)

DC Output Current, per pin (IOUT)

±35 mA

IN OUT

−40

+85

°C

Operating Temperature Range (T )

DC VCC or GND Current, per pin (ICC)

±70 mA

A

Input Rise or Fall Times

Storage Temperature Range (TSTG)

−65°C to +150°C

(t

, t )

V

CC

= 2.0V

1000

ns

Power Dissipation (PD)

r

f

VCC = 4.5V

500

ns

(Note 3)

600 mW

VCC = 6.0V

400

ns

S.O. Package only

500 mW

Note 1: Maximum Ratings are those values beyond which damage to the

Lead Temperature (TL)

device may occur.

260°C

Note 2: Unless otherwise specified all voltages are referenced to ground.

(Soldering 10 seconds)

Note 3: Power Dissipation temperature derating — plastic “N” package: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics

(Note 4)

Symbol

Parameter

Conditions

VCC

TA = 25°C

TA = −40 to 85°C

TA = −55 to 125°C

Units

Typ

Guaranteed Limits

VIH

Minimum HIGH Level Input

2.0V

1.5

1.5

1.5

V

Voltage

4.5V

3.15

3.15

3.15

V

6.0V

4.2

4.2

4.2

V

VIL

Maximum LOW Level Input

2.0V

0.5

0.5

0.5

V

Voltage

4.5V

1.35

1.35

1.35

V

6.0V

1.8

1.8

1.8

V

VOH

Minimum HIGH Level Output

VIN = VIH or VIL

Voltage

|IOUT| ≤ 20 μA

2.0V

2.0

1.9

1.9

1.9

V

4.5V

4.5

4.4

4.4

4.4

V

6.0V

6.0

5.9

5.9

5.9

V

VIN = VIH or VIL

|IOUT| ≤ 6.0 mA

4.5V

4.2

3.98

3.84

3.7

V

|IOUT| ≤ 7.8 mA

6.0V

5.7

5.48

5.34

5.2

V

VOL

Maximum LOW Level Output

VIN = VIH or VIL

Voltage

|IOUT| ≤ 20 μA

2.0V

0

0.1

0.1

0.1

V

4.5V

0

0.1

0.1

0.1

V

6.0V

0

0.1

0.1

0.1

V

VIN = VIH or VIL

|IOUT| ≤ 6.0 mA

4.5V

0.2

0.26

0.33

0.4

V

|IOUT| ≤ 7.8 mA

6.0V

0.2

0.26

0.33

0.4

V

IIN

Maximum Input Current

VIN = VCC or GND

6.0V

±0.1

±1.0

±1.0

μA

IOZ

Maximum 3-STATE

VOUT = VCC or GND

Output Leakage Current

OC = VIH

6.0V

±0.5

±5.0

±10

μA

ICC

Maximum Quiescent Supply

VIN = VCC or GND

Current

IOUT = 0 μA

6.0V

8.0

80

160

μA

ICC

Quiescent Supply Current

VCC = 5.5V

OE

1.0

1.5

1.8

2.0

mA

per Input Pin

VIN = 2.4V

CLK

0.6

0.8

1.0

1.1

mA

or 0.4V (Note 4)

DATA

0.4

0.5

0.6

0.7

mA

Note 4: For a power supply of 5V ±10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when

designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage cur-

rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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AC Electrical Characteristics

VCC = 5V, TA = 25°C, tr = tf = 6 ns

	Symbol	Parameter	Conditions	Typ	Guaranteed	Units
					Limit
	fMAX	Maximum Operating Frequency		60	33	MHz
	tPHL, tPLH	Maximum Propagation Delay, Clock to Q	CL = 45 pF	17	27	ns
	tPZH, tPZL	Maximum Output Enable Time	RL = 1 kΩ	19	28	ns
			CL = 45 pF
	tPHZ, tPLZ	Maximum Output Disable Time	RL = 1 kΩ	14	25	ns
			CL = 5 pF
	tS	Minimum Setup Time, Data to Clock		10	12	ns
	tH	Minimum Hold Time, Clock to Data		−3	5	ns
	tW	Minimum Pulse Clock Width		8	15	ns

AC Electrical Characteristics

VCC = 2.0 − 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol	Parameter	Conditions	VCC	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
				Typ		Guaranteed Limits
fMAX	Maximum Operating Frequency	CL = 50 pF	2.0V		33	28	23	MHz
			4.5V		30	24	20	MHz
			6.0V		35	28	23	MHz
tPHL, tPLH	Maximum Propagation	CL = 50 pF	2.0V	18	30	38	45	ns
	Delay, Clock to Q	CL = 150 pF	2.0V	51	155	194	233	ns
		CL = 50 pF	4.5V	13	23	29	35	ns
		CL = 150 pF	4.5V	19	31	47	47	ns
		CL = 50 pF	6.0V	12	20	25	30	ns
		CL = 150 pF	6.0V	18	27	34	41	ns
tPZH, tPZL	Maximum Output Enable	RL = 1 kΩ
	Time	CL = 50 pF	2.0V	22	30	38	45	ns
		CL = 150 pF	2.0V	59	180	225	270	ns
		CL = 50 pF	4.5V	14	28	35	42	ns
		CL = 150 pF	4.5V	20	36	45	54	ns
		CL = 50 pF	6.0V	12	24	30	36	ns
		CL = 150 pF	6.0V	18	31	39	47	ns
tPHZ, tPLZ	Maximum Output Disable Time	RL = 1 kΩ	2.0V	15	30	38	45	ns
		CL = 50 pF	4.5V	12	25	31	38	ns
			6.0V	10	21	27	32	ns
tS	Minimum Setup Time		2.0V	6	12	15	18	ns
	Data to Clock		4.5V		20	25	30	ns
			6.0V		17	21	25	ns
tH	Minimum Hold Time		2.0V	−1	5	6	8	ns
	Clock to Data		4.5V		0	0	0	ns
			6.0V		0	0	0	ns
tTHL, tTLH	Maximum Output Rise	CL = 50 pF	2.0V	6	12	15	18	ns
	and Fall Time		4.5V	7	12	15	18	ns
			6.0V	6	10	13	15	ns
tW	Minimum Clock Pulse Width		2.0V	30	15	20	24	ns
			4.5V	9	16	20	24	ns
			6.0V	8	14	18	20	ns
tr,tf	Maximum Clock Input Rise		2.0V		1000	1000	1000	ns
	and Fall Time		4.5V		500	500	500	ns
			6.0V		400	400	400	ns
CPD	Power Dissipation Capacitance	OC = VCC		5				pF
	(Note 5) (per latch)	OC = GND		58				pF
CIN	Maximum Input Capacitance			5	10	10	10	pF

MM74HC574

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