Fairchild Semiconductor MM74HCT540WM, MM74HCT540WMX, MM74HCT540MTCX, MM74HCT540N, MM74HCT540SJ Datasheet
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February 1984
Revised February 1999
MM74HCT540 • MM74HCT541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HCT540 and MM74HCT541 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed inverting and non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the low power consumption of CMOS. Both devices are TTL input compatible and have a fanout of 15 LS-TTL equivalent inputs.
MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
The MM74HCT540 is an inverting buffer and the MM74HCT541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high-imped- ance state.
In order to enhance PC board layout, the MM74HCT540 and MM74HCT541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
■TTL input compatible
■Typical propagation delay: 12 ns
■3-STATE outputs for connection to system buses
■Low quiescent current: 80 μA
■Output current: 6 mA (min.)
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HCT540WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74HCT540SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HCT540MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HCT540N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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MM74HCT541WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74HCT541SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HCT541MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HCT541N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View |
Top View |
MM74HCT540 |
MM74HCT541 |
Buffer STATE-3 Octal • Buffer STATE-3 Octal Inverting MM74HCT541 • MM74HCT540
© 1999 Fairchild Semiconductor Corporation |
DS006040.prf |
www.fairchildsemi.com |
MM74HCT540 • MM74HCT541
Absolute Maximum Ratings(Note 1)
(Note 2) |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Clamp Diode Current (IIK, IOK) |
±20 mA |
DC Output Current, per pin (IOUT) |
±35 mA |
DC VCC or GND Current, per pin (ICC) |
±70 mA |
Storage Temperature Range (TSTG) |
−65°C to +150°C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
260°C |
(Soldering 10 seconds) |
Recommended Operating
Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
4.5 |
5.5 |
V |
DC Input or Output Voltage |
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(VIN, VOUT) |
0 |
VCC |
V |
Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise or Fall Times |
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(tr, tf) |
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500 |
ns |
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
VCC = 5V ± 10% (unless otherwise specified) |
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Symbol |
Parameter |
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Conditions |
TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
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2.0 |
2.0 |
2.0 |
V |
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Input Voltage |
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VIL |
Maximum LOW Level |
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0.8 |
0.8 |
0.8 |
V |
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Input Voltage |
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VOH |
Minimum HIGH Level |
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VIN = VIH or VIL |
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Output Voltage |
|IOUT| = 20 μA |
VCC |
VCC− 0.1 |
VCC− 0.1 |
VCC− 0.1 |
V |
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|IOUT| = 6.0 mA, VCC = 4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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|IOUT| = 7.2 mA, VCC = 5.5V |
5.2 |
4.98 |
4.84 |
4.7 |
V |
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VOL |
Maximum LOW Level |
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VIN = VIH or VIL |
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Voltage |
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|IOUT| = 20 μA |
0 |
0.1 |
0.1 |
0.1 |
V |
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|IOUT| = 6.0 mA, VCC = 4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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|IOUT| = 7.2 mA, VCC = 5.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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IIN |
Maximum Input |
VIN = VCC or GND |
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±0.1 |
±1.0 |
±1.0 |
μA |
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Current |
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IOZ |
Maximum 3-STATE |
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VOUT = VCC or GND |
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±0.5 |
±5.0 |
±10 |
μA |
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Output Leakage |
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= VIH |
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G |
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Current |
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ICC |
Maximum Quiescent |
VIN = VCC or GND |
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8.0 |
80 |
160 |
μA |
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Supply Current |
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IOUT = 0 μA |
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VIN = 2.4V or 0.5V (Note 4) |
0.6 |
1.0 |
1.3 |
1.5 |
mA |
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Note 4: Measured per input. All other inputs at VCC or GND.
www.fairchildsemi.com |
2 |
AC Electrical Characteristics
MM74HCT540: VCC = 5.0V, tr = tf = 6 ns, TA = 25°C, (unless otherwise specified)
Symbol |
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Parameter |
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Conditions |
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Typ |
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Guaranteed |
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Units |
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Limits |
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tPHL, tPLH |
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Maximum Output |
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CL = 45 pF |
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12 |
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18 |
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ns |
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Propagation Delay |
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tPZL, tPZH |
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Maximum Output |
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CL = 45 pF |
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14 |
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28 |
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ns |
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Enable Time |
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RL = 1 kΩ |
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tPLZ, tPHZ |
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Maximum Output |
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CL = 5 pF |
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13 |
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25 |
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ns |
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Disable Time |
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RL = 1 kΩ |
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AC Electrical Characteristics |
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MM74HCT540: VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified) |
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Symbol |
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Parameter |
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Conditions |
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TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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tPHL, tPLH |
Maximum Output |
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CL = 50 pF |
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12 |
20 |
25 |
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30 |
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ns |
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Propagation Delay |
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CL = 150 pF |
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22 |
30 |
38 |
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45 |
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ns |
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tPZH, tPZL |
Maximum Output |
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RL = 1 kΩ |
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CL = 50 pF |
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15 |
30 |
38 |
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45 |
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ns |
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Enable Time |
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CL = 150 pF |
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20 |
40 |
50 |
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60 |
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ns |
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tPHZ, tPLZ |
Maximum Output |
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RL = 1 kΩ |
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15 |
30 |
38 |
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45 |
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ns |
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Disable Time |
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CL = 50 pF |
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tTHL, tTLH |
Maximum Output |
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CL = 50 pF |
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6 |
12 |
15 |
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18 |
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ns |
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Rise and Fall Time |
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CIN |
Maximum Input |
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5 |
10 |
10 |
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10 |
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pF |
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Capacitance |
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COUT |
Maximum Output |
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15 |
20 |
20 |
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20 |
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pF |
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Capacitance |
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CPD |
Power Dissipation |
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(per output) |
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= VCC |
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12 |
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pF |
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G |
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Capacitance (Note 5) |
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= GND |
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50 |
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pF |
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G |
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Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC,and the no load dynamic current consumption, IS = CPD VCC f + ICC.
MM74HCT541 • MM74HCT540
3 |
www.fairchildsemi.com |
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