September 1983
Revised February 1999
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate CMOS technology. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity, and low power consumption. Both devices have a fanout of 15 LS-TTL equivalent inputs.
The MM74HC540 is an inverting buffer and the MM74HC541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high-imped- ance state.
In order to enhance PC board layout, the MM74HC540 and MM74HC541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
■Typical propagation delay: 12 ns
■3-STATE outputs for connection to system buses
■Wide power supply range: 2–6V
■Low quiescent current: 80 μA maximum (74HC Series)
■Output current: 6 mA
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC540WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74HC540SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC540MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC540N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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MM74HC541WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74HC541SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC541MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC541N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View |
Top View |
MM74HC540 |
MM74HC541 |
Buffer STATE-3 Octal • Buffer STATE-3 Octal Inverting MM74HC541 • MM74HC540
© 1999 Fairchild Semiconductor Corporation |
DS005341.prf |
www.fairchildsemi.com |
MM74HC540 • MM74HC541
Absolute Maximum Ratings(Note 1)
(Note 2) |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Clamp Diode Current (ICD) |
±20 mA |
DC Output Current, per pin (IOUT) |
±35 mA |
DC VCC or GND Current, |
±70 mA |
per pin (ICC) |
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Storage Temperature Range (TSTG) |
−65°C to +150°C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
260°C |
(Soldering 10 seconds) |
DC Electrical Characteristics (Note 4)
Recommended Operating
Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
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(VIN, VOUT) |
0 |
VCC |
V |
Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise or Fall Times |
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(tr, tf) VCC = 2.0V |
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1000 |
ns |
VCC = 4.5V |
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500 |
ns |
VCC = 6.0V |
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400 |
ns |
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
Symbol |
Parameter |
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Conditions |
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VCC |
TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
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2.0V |
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1.5 |
1.5 |
1.5 |
V |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
V |
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VIL |
Maximum LOW Level |
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2.0V |
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0.5 |
0.5 |
0.5 |
V |
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Input Voltage |
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4.5V |
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1.35 |
1.35 |
1.35 |
V |
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6.0V |
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1.8 |
1.8 |
1.8 |
V |
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VOH |
Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
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2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
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4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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|IOUT| ≤ 7.8 mA |
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6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
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VOL |
Maximum LOW Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
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2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
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4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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|IOUT| ≤ 7.8 mA |
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6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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IIN |
Maximum Input |
VIN = VCC or GND |
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6.0V |
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±0.1 |
±1.0 |
±1.0 |
μA |
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Current |
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IOZ |
Maximum 3-STATE |
V |
= V or V |
, |
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= V |
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6.0V |
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±0.5 |
±5 |
±10 |
μA |
G |
IH |
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IN |
IH |
IL |
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Output Leakage |
VOUT = VCC or GND |
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Current |
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ICC |
Maximum Quiescent |
VIN = VCC or GND |
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6.0V |
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8.0 |
80 |
160 |
μA |
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Supply Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
www.fairchildsemi.com |
2 |