Fairchild Semiconductor MM74HC174MX, MM74HC174N, MM74HC174SJ, MM74HC174MTC, MM74HC174M Datasheet
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September 1983
Revised February 1999
MM74HC174
Hex D-Type Flip-Flops with Clear
General Description
The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
■Typical propagation delay: 16 ns
■Wide operating voltage range: 2–6V
■Low input current: 1 μA maximum
■Low quiescent current: 80 μA (74HC Series)
■Output drive: 10 LSTTL loads
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC174M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
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MM74HC174SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC174MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC174N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
(Each Flip-Flop)
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Inputs |
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Outputs |
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Clear |
Clock |
D |
Q |
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L |
X |
X |
L |
H |
− |
H |
H |
H |
− |
L |
L |
H |
L |
X |
Q0 |
H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care
− = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady state input conditions were established.
Clear with Flops-Flip Type-D Hex MM74HC174
© 1999 Fairchild Semiconductor Corporation |
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www.fairchildsemi.com |
MM74HC174
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Clamp Diode Current (IIK, IOK) |
±20 mA |
DC Output Current, per pin (IOUT) |
±25 mA |
DC VCC or GND Current, per pin (ICC) |
±50 mA |
Storage Temperature Range (TSTG) |
−65°C to +150°C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
260°C |
(Soldering 10 seconds) |
Recommended Operating
Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
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(VIN, VOUT) |
0 |
VCC |
V |
Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise or Fall Times |
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(tr, tf) VCC = 2.0V |
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1000 |
ns |
VCC = 4.5V |
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500 |
ns |
VCC = 6.0V |
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400 |
ns |
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics |
(Note 4) |
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Symbol |
Parameter |
Conditions |
VCC |
TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
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2.0V |
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1.5 |
1.5 |
1.5 |
V |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
V |
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VIL |
Maximum LOW Level |
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2.0V |
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0.5 |
0.5 |
0.5 |
V |
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Input Voltage |
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4.5V |
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1.35 |
1.35 |
1.35 |
V |
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6.0V |
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1.8 |
1.8 |
1.8 |
V |
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VOH |
Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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|IOUT| ≤ 5.2 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
VOL |
Maximum LOW Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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|IOUT| ≤ 5.2 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
IIN |
Maximum Input |
VIN = VCC or GND |
6.0V |
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±0.1 |
±1.0 |
±1.0 |
μA |
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Current |
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ICC |
Maximum Quiescent |
VIN = VCC or GND |
6.0V |
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8.0 |
80 |
160 |
μA |
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Supply Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
MM74HC174
3 |
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