Fairchild Semiconductor MM74HC393N, MM74HC393SJ, MM74HC393SJX, MM74HC393CW, MM74HC393M Datasheet

September 1983

Revised February 1999

MM74HC393

Dual 4-Bit Binary Counter

General Description

The MM74HC393 counter circuits contain independent ripple carry counters and utilize advanced silicon-gate CMOS technology. The MM74HC393 contains two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter.

Each of the two 4-bit counters is incremented on the HIGH- to-LOW transition (negative edge) of the clock input, and each has an independent clear input. When clear is set HIGH all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations.

Each of the counters outputs can drive 10 low power Schottky TTL equivalent loads. This counter is functionally

as well as pin equivalent to the 74LS393. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features

■Typical operating frequency: 50 MHz

■Typical propagation delay: 13 ns (Ck to QA)

■Wide operating supply voltage range: 2–6V

■Low input current: <1 μA

■Low quiescent supply current: 80 μA maximum (74HC Series)

■Fanout of 10 LS-TTL loads

Ordering Code:

Order Number	Package Number	Package Description
MM74HC393M	M14A	14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC393SJ	M14D	14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC393MTC	MTC14	14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC393N	N14A	14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Counter Binary Bit-4 Dual MM74HC393

© 1999 Fairchild Semiconductor Corporation

DS005337.prf

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MM74HC393

Absolute Maximum Ratings

(Note 2)
(Note 1)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC +1.5V
DC Output Voltage (VOUT)	−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)	±20 mA
DC Output Current, per pin (IOUT)	±25 mA
DC VCC or GND Current, per pin (ICC)	±50 mA
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

DC Electrical Characteristics (Note 4)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	2	6	V
DC Input or Output Voltage
(VIN, VOUT)	0	VCC	V
Operating Temperature Range (TA)	−40	+85	°C
Input Rise or Fall Times
(tr, tf) VCC = 2.0V		1000	ns
VCC = 4.5V		500	ns
VCC = 6.0V		400	ns

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

Symbol	Parameter	Conditions	VCC	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
				Typ		Guaranteed Limits
VIH	Minimum HIGH Level		2.0V		1.5	1.5	1.5	V
	Input Voltage		4.5V		3.15	3.15	3.15	V
			6.0V		4.2	4.2	4.2	V
VIL	Maximum LOW Level		2.0V		0.5	0.5	0.5	V
	Input Voltage		4.5V		1.35	1.35	1.35	V
			6.0V		1.8	1.8	1.8	V
VOH	Minimum HIGH Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	2.0	1.9	1.9	1.9	V
			4.5V	4.5	4.4	4.4	4.4	V
			6.0V	6.0	5.9	5.9	5.9	V
		VIN = VIH or VIL
		|IOUT| ≤ 4.0 mA	4.5V	4.2	3.98	3.84	3.7	V
		|IOUT| ≤ 5.2 mA	6.0V	5.7	5.48	5.34	5.2	V
VOL	Maximum LOW Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	0	0.1	0.1	0.1	V
			4.5V	0	0.1	0.1	0.1	V
			6.0V	0	0.1	0.1	0.1	V
		VIN = VIH or VIL
		|IOUT| ≤ 4.0 mA	4.5V	0.2	0.26	0.33	0.4	V
		|IOUT| ≤ 5.2 mA	6.0V	0.2	0.26	0.33	0.4	V
IIN	Maximum Input	VIN = VCC or GND	6.0V		±0.1	±1.0	±1.0	μA
	Current
ICC	Maximum Quiescent	VIN = VCC or GND	6.0V		8.0	80	160	μA
	Supply Current	IOUT = 0 μA

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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AC Electrical Characteristics

VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns

	Symbol	Parameter	Conditions	Typ	Guaranteed	Units
					Limit
	fMAX	Maximum Operating Frequency		50	30	MHz
	tPHL, tPLH	Maximum Propagation Delay, Clock A to QA		13	20	ns
	tPHL, tPLH	Maximum Propagation Delay, Clock A to QB		19	35	ns
	tPHL, tPLH	Maximum Propagation Delay, Clock A to QC		23	42	ns
	tPHL, tPLH	Maximum Propagation Delay, Clock A to QD		27	50	ns
	tPHL	Maximum Propagation Delay, Clear to any Q		15	28	ns
	tREM	Minimum Removal Time		−2	5	ns
	tW	Minimum Pulse Width Clear or Clock		10	16	ns

AC Electrical Characteristics

CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)

Symbol	Parameter	Conditions	VCC	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
				Typ		Guaranteed Limits
fMAX	Maximum Operating		2.0V		5	4	3
	Frequency		4.5V		27	21	18	MHz
			6.0V		31	24	20	MHz
tPHL, tPLH	Maximum Propagation		2.0V	45	120	150	180	ns
	Delay Clock A to QA		4.5V	15	24	30	35	ns
			6.0V	13	21	26	31	ns
tPHL, tPLH	Maximum Propagation		2.0V	68	190	240	285	ns
	Delay Clock A to QB		4.5V	23	38	47	57	ns
			6.0V	20	32	40	48	ns
tPHL, tPLH	Maximum Propagation		2.0V	90	240	300	360	ns
	Delay Clock A to QC		4.5V	30	48	60	72	ns
			6.0V	26	41	51	61	ns
tPHL, tPLH	Maximum Propagation Delay		2.0V	100	290	360	430	ns
	Clock to QD		4.5V	35	58	72	87	ns
			6.0V	30	50	62	75	ns
tPHL	Maximum Propagation		2.0V	54	165	210	250	ns
	Delay Clear to any Q		4.5V	18	33	41	49	ns
			6.0V	15	28	35	42	ns
tREM	Minimum Clear		2.0V		25	25	25	ns
	Removal Time		4.5V		5	5	5	ns
			6.0V		5	5	5	ns
tW	Minimum Pulse Width		2.0V	30	80	100	120	ns
	Clear or Clock		4.5V	10	16	20	24	ns
			6.0V	9	14	18	20	ns
tTHL, tTLH	Maximum Output		2.0V	30	75	95	110	ns
	Rise and Fall Time		4.5V	8	15	19	22	ns
			6.0V	7	13	16	19	ns
tr, tf	Maximum Input				1000	1000	1000	ns
	Rise and Fall Time				500	500	500	ns
					400	400	400	ns
CPD	Power Dissipation	(per counter)		42				pF
	Capacitance (Note 5)
CIN	Maximum Input Capacitance			5	10	10	10	pF

Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.

MM74HC393

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