Fairchild Semiconductor MM74HCT374MTC, MM74HCT374N, MM74HCT374SJ, MM74HCT374SJX, MM74HCT374WM Datasheet
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February 1984
Revised February 1999
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic & pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground.
When the MM74HCT373 LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
Features
■TTL input characteristic compatible
■Typical propagation delay: 20 ns
■Low input current: 1 μA maximum
■Low quiescent current: 80 μA maximum
■Compatible with bus-oriented systems
■Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number |
Package Number |
Package Descriptions |
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MM74HCT373WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74HCT373SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HCT373MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HCT373N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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MM74HCT373WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74HCT373SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HCT373MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HCT373N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Flop-Flip Type-D Octal STATE-3 • Latch Type-D Octal STATE-3 MM74HCT374 • MM74HCT373
© 1999 Fairchild Semiconductor Corporation |
DS005367.prf |
www.fairchildsemi.com |
MM74HCT373 • MM74HCT374
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View |
Top View |
MM74HCT373 |
MM74HCT374 |
Truth Tables
MM74HCT373
Output |
LE |
Data |
373 |
Control |
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Output |
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L |
H |
H |
H |
L |
H |
L |
L |
L |
L |
X |
Q0 |
H |
X |
X |
Z |
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MM74HCT374
Output |
Clock |
Data |
Output |
Control |
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(374) |
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L |
− |
H |
H |
L |
− |
L |
L |
L |
L |
X |
Q0 |
H |
X |
X |
Z |
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H = HIGH Level |
H = HIGH Level |
L = LOW Level |
L = LOW Level |
Q0 = Level of output before steady-state input conditions were established. |
X = Don’t Care |
Z = High Impedance |
− = Transition from LOW-to-HIGH |
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Z = High Impedance State |
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Q0 = The level of the output before steady state input conditions were |
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established. |
www.fairchildsemi.com |
2 |
Logic Diagrams
MM74HCT373
MM74HCT374
MM74HCT374 • MM74HCT373
3 |
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