Fairchild Semiconductor MM74HC138N, MM74HC138SJ, MM74HC138SJX, MM74HC138M, MM74HC138MTC Datasheet

September 1983

Revised February 1999

MM74HC138

3-to-8 Line Decoder

General Description

The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic.

The MM74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders.

The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features

■Typical propagation delay: 20 ns

■Wide power supply range: 2V–6V

■Low quiescent current: 80 μA maximum (74HC Series)

■Low input current: 1 μA maximum

■Fanout of 10 LS-TTL loads

Ordering Code:

Order Number	Package Number	Package Description
MM74HC138M	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC138SJ	M16D	16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC138MTC	MTC16	16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC138N	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignment for DIP, SOIC, SOP and TSSOP

Decoder Line 8-to-3 MM74HC138

© 1999 Fairchild Semiconductor Corporation

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MM74HC138

Truth Table

Inputs

Outputs

Enable

Select

G1

G2 (Note 1)

C

B

A

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

X

H

X

X

X

H

H

H

H

H

H

H

H

L

X

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

L

L

H

H

H

H

H

H

H

H

L

L

L

H

H

L

H

H

H

H

H

H

H

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

H

H

H

H

H

L

H

H

H

H

H

L

H

L

L

H

H

H

H

L

H

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

H

L

H

H

L

H

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

L

H = HIGH Level, L = LOW Level, X = don’t care

Note 1: G2 = G2A+G2B

Logic Diagram

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2

DC Output Voltage (VOUT)

− 0.5 to VCC + 0.5V

DC Input or Output Voltage

0

V

V

MM74HC138

Absolute Maximum Ratings(Note 2)

Recommended Operating

(Note 3)

Conditions

Supply Voltage (VCC)

− 0.5 to + 7.0V

Min

Max

Units

DC Input Voltage (VIN)

− 1.5 to VCC + 1.5V

Supply Voltage (VCC)

2

6

V

Clamp Diode Current (IIK, IOK)

± 20 mA

CC

(V

IN

, V

OUT

)

DC Output Current, per pin (IOUT)

± 25 mA

−40

+85

°C

Operating Temperature Range (TA)

DC VCC or GND Current, per pin (ICC)

± 50 mA

Input Rise or Fall Times

Storage Temperature Range (TSTG)

− 65°C to + 150°C

(t , t ) V

CC

= 2.0V

1000

ns

Power Dissipation (PD)

r

f

VCC = 4.5V

500

ns

(Note 4)

600 mW

VCC = 6.0V

400

ns

S.O. Package only

500 mW

Note 2: Absolute Maximum Ratings are those values beyond which dam-

Lead Temperature (TL)

age to the device may occur.

260°C

Note 3: Unless otherwise specified all voltages are referenced to ground.

(Soldering 10 seconds)

Note 4: Power Dissipation temperature derating — plastic “N” package: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 5)

Symbol

Parameter

Conditions

VCC

TA = 25°C

TA = −40 to 85°C

Units

Typ

Guaranteed Limits

VIH

Minimum HIGH Level

2.0V

1.5

1.5

V

Input Voltage

4.5V

3.15

3.15

V

6.0V

4.2

4.2

V

VIL

Maximum LOW Level

2.0V

0.5

0.5

V

Input Voltage

4.5V

1.35

1.35

V

6.0V

1.8

1.8

V

VOH

Minimum HIGH Level

VIN = VIH or VIL

Output Voltage

| IOUT | ≤ 20 μA

2.0V

2.0

1.9

1.9

V

4.5V

4.5

4.4

4.4

V

6.0V

6.0

5.9

5.9

V

VIN = VIH or VIL

|IOUT | ≤ 4.0 mA

4.5V

4.2

3.98

3.84

V

| IOUT | ≤ 5.2 mA

6.0V

5.7

5.48

5.34

V

VOL

Maximum LOW Level

VIN = VIH or VIL

Output Voltage

| IOUT | ≤ 20 μA

2.0V

0

0.1

0.1

V

4.5V

0

0.1

0.1

V

6.0V

0

0.1

0.1

V

VIN = VIH or VIL

| IOUT | ≤ 4.0 mA

4.5V

0.2

0.26

0.33

V

| IOUT | ≤ 5.2 mA

6.0V

0.2

0.26

0.33

V

IIN

Maximum Input

VIN = VCC or GND

6.0V

±0.1

±1.0

μA

Current

ICC

Maximum Quiescent

VIN = VCC or GND

6.0V

8.0

80

μA

Supply Current

IOUT = 0 μA

Note 5: For

a power supply of 5V ± 10% the worst

case output voltages (VOH, and VOL)

occur for HC

at 4.5V. Thus the 4.5V values should be used when

designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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