Fairchild Semiconductor MM74HC00N, MM74HC00SJ, MM74HC00SJX, MM74HC00MTCX, MM74HC00CW Datasheet
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September 1983
Revised February 1999
MM74HC00
Quad 2-Input NAND Gate
General Description
The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to
static discharge by internal diode clamps to VCC and ground.
Features
■Typical propagation delay: 8 ns
■Wide power supply range: 2–6V
■Low quiescent current: 20 μA maximum (74HC Series)
■Low input current: 1 μA maximum
■Fanout of 10 LS-TTL loads
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC00M |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
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MM74HC00SJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC00MTC |
MTC14 |
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC00N |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Logic Diagram |
Pin Assignments for DIP, SOIC, SOP and TSSOP |
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Top View
Gate NAND Input-2 Quad MM74HC00
© 1999 Fairchild Semiconductor Corporation |
DS005292.prf |
www.fairchildsemi.com |
MM74HC00 |
DC Input Voltage (VIN) |
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−1.5 to VCC+1.5V |
Supply Voltage (VCC) |
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2 |
6 |
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V |
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Absolute Maximum Ratings(Note 1) |
Recommended Operating |
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(Note 2) |
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Conditions |
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Supply Voltage (VCC) |
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−0.5 to +7.0V |
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Min |
Max |
Units |
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DC Output Voltage (VOUT) |
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−0.5 to VCC+0.5V |
DC Input or Output Voltage |
0 |
VCC |
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V |
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Clamp Diode Current (IIK, IOK) |
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±20 mA |
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(V |
IN |
, V |
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) |
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DC Output Current, per pin (IOUT) |
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±25 mA |
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OUT |
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−40 |
+85 |
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°C |
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Operating Temperature Range (TA) |
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DC VCC or GND Current, per pin (ICC) |
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±50 mA |
Input Rise or Fall Times |
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Storage Temperature Range (TSTG) |
−65°C to +150°C |
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(t , t ) |
V |
CC |
= 2V |
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1000 |
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ns |
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Power Dissipation (PD) |
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VCC = 4.5V |
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500 |
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ns |
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(Note 3) |
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600 mW |
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VCC = 6.0V |
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400 |
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ns |
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S.O. Package only |
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500 mW |
Note 1: Absolute Maximum Ratings are those values beyond which dam- |
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Lead Temperature (TL) |
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age to the device may occur. |
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260°C |
Note 2: Unless otherwise specified all voltages are referenced to ground. |
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(Soldering 10 seconds) |
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Note 3: Power Dissipation temperature derating — plastic “N” package: − |
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12 mW/°C from 65°C to 85°C. |
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DC Electrical Characteristics |
(Note 4) |
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Symbol |
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Parameter |
Conditions |
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VCC |
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TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
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Minimum HIGH Level |
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2.0V |
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1.5 |
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1.5 |
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1.5 |
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V |
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Input Voltage |
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4.5V |
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3.15 |
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3.15 |
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3.15 |
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V |
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6.0V |
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4.2 |
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4.2 |
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4.2 |
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V |
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VIL |
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Maximum LOW Level |
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2.0V |
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0.5 |
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0.5 |
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0.5 |
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V |
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Input Voltage |
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4.5V |
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1.35 |
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1.35 |
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1.35 |
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V |
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6.0V |
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1.8 |
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1.8 |
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1.8 |
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V |
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VOH |
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Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
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2.0V |
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2.0 |
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1.9 |
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1.9 |
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1.9 |
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V |
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4.5V |
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4.5 |
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4.4 |
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4.4 |
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4.4 |
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V |
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6.0V |
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6.0 |
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5.9 |
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5.9 |
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5.9 |
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V |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
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4.5V |
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4.2 |
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3.98 |
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3.84 |
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3.7 |
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V |
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|IOUT| ≤ 5.2 mA |
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6.0V |
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5.7 |
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5.48 |
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5.34 |
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5.2 |
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V |
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VOL |
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Maximum LOW Level |
VIN = VIH |
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Output Voltage |
|IOUT| ≤ 20 μA |
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2.0V |
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0 |
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0.1 |
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0.1 |
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0.1 |
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V |
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4.5V |
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0 |
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0.1 |
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0.1 |
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0.1 |
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V |
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6.0V |
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0 |
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0.1 |
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0.1 |
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0.1 |
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V |
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VIN = VIH |
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|IOUT| ≤ 4.0 mA |
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4.5V |
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0.2 |
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0.26 |
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0.33 |
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0.4 |
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V |
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|IOUT| ≤ 5.2 mA |
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6.0V |
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0.2 |
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0.26 |
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0.33 |
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0.4 |
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V |
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IIN |
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Maximum Input |
VIN = VCC or GND |
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6.0V |
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±0.1 |
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±1.0 |
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±1.0 |
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μA |
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Current |
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ICC |
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Maximum Quiescent |
VIN = VCC or GND |
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6.0V |
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2.0 |
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20 |
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40 |
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μA |
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Supply Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when |
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designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur- |
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rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. |
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www.fairchildsemi.com |
2 |
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