Fairchild Semiconductor MM74HC151M, MM74HC151MTC, MM74HC151MTCX, MM74HC151SJ, MM74HC151MX Datasheet
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September 1983
Revised February 1999
MM74HC151
8-Channel Digital Multiplexer
General Description
The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation of standard CMOS integrated circuits, it possesses the ability to drive 10 LS-TTL loads. The MM74HC151 selects one of the 8 data sources, depending on the address presented on the A, B, and C inputs. It features both true (Y) and complement (W) outputs. The STROBE input must be at a low logic level to enable this multiplexer. A high logic level at the STROBE forces the W output HIGH and the Y output LOW.
The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
■Typical propagation delay data select to output Y: 26 ns
■Wide operating supply voltage range: 2–6V
■Low input current: 1 μA maximum
■Low quiescent supply current: 80 μA maximum (74HC)
■High output drive current: 4 mA minimum
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC151M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
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MM74HC151SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC151MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC151N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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Pin Assignments for DIP, SOIC, SOP and TSSOP |
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Inputs |
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Outputs |
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Select |
Strobe |
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C |
B |
A |
S |
Y |
W |
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X |
X |
X |
H |
L |
H |
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L |
L |
L |
L |
D0 |
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D0 |
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L |
L |
H |
L |
D1 |
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D1 |
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L |
H |
L |
L |
D2 |
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D2 |
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L |
H |
H |
L |
D3 |
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D3 |
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H |
L |
L |
L |
D4 |
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D4 |
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H |
L |
H |
L |
D5 |
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D5 |
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H |
H |
L |
L |
D6 |
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D6 |
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H |
H |
H |
L |
D7 |
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D7 |
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Top View |
H = HIGH Level, L = LOW Level, X = Don't Care |
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D0, D1...D7 = the level of the respective D input |
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Multiplexer Digital Channel-8 MM74HC151
© 1999 Fairchild Semiconductor Corporation |
DS005313.prf |
www.fairchildsemi.com |
MM74HC151
Logic Diagram
www.fairchildsemi.com |
2 |
DC Output Voltage (VOUT) |
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−0.5 to VCC +0.5V |
DC Input or Output Voltage |
0 |
VCC |
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V |
MM74HC151 |
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Absolute Maximum Ratings(Note 1) |
Recommended Operating |
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(Note 2) |
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Conditions |
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Supply Voltage (VCC) |
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−0.5 to +7.0V |
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Min |
Max |
Units |
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DC Input Voltage (VIN) |
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−1.5 to VCC +1.5V |
Supply Voltage (V |
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2 |
6 |
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V |
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CC |
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Clamp Diode Current (IIK, IOK) |
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±20 mA |
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(V |
, V |
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DC Output Current, per pin (IOUT) |
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±25 mA |
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IN |
OUT |
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−40 |
+85 |
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°C |
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Operating Temperature Range (TA) |
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DC VCC or GND Current, per pin (ICC) |
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±50 mA |
Input Rise or Fall Times |
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Storage Temperature Range (TSTG) |
−65°C to +150°C |
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(t |
, t ) V |
CC |
= 2.0V |
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1000 |
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ns |
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Power Dissipation (PD) |
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r |
f |
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VCC = 4.5V |
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500 |
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ns |
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(Note 3) |
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600 mW |
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VCC = 6.0V |
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400 |
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ns |
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S.O. Package only |
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500 mW |
Note 1: Absolute Maximum Ratings are those values beyond which dam- |
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Lead Temperature (TL) |
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260°C |
age to the device may occur. |
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Note 2: Unless otherwise specified all voltages are referenced to ground. |
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(Soldering 10 seconds) |
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Note 3: Power Dissipation temperature derating — plastic “N” package: − |
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12 mW/°C from 65°C to 85°C. |
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DC Electrical Characteristics |
(Note 4) |
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Symbol |
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Parameter |
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Conditions |
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VCC |
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TA = 25°C |
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TA = −40 to 85°C |
TA = −55 to 125°C |
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Units |
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Typ |
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Guaranteed Limits |
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VIH |
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Minimum HIGH Level |
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2.0V |
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1.5 |
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1.5 |
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1.5 |
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V |
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Input Voltage |
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4.5V |
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3.15 |
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3.15 |
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3.15 |
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V |
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6.0V |
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4.2 |
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4.2 |
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4.2 |
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V |
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VIL |
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Maximum LOW Level |
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2.0V |
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0.5 |
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0.5 |
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0.5 |
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V |
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Input Voltage |
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4.5V |
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1.35 |
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1.35 |
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1.35 |
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V |
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6.0V |
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1.8 |
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1.8 |
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1.8 |
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V |
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VOH |
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Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
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2.0V |
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2.0 |
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1.9 |
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1.9 |
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1.9 |
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V |
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4.5V |
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4.5 |
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4.4 |
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4.4 |
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4.4 |
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V |
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6.0V |
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6.0 |
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5.9 |
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5.9 |
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5.9 |
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V |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
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4.5V |
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4.2 |
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3.98 |
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3.84 |
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3.7 |
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V |
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|IOUT| ≤ 5.2 mA |
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6.0V |
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5.7 |
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5.48 |
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5.34 |
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5.2 |
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V |
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VOL |
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Maximum LOW Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
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2.0V |
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0 |
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0.1 |
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0.1 |
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0.1 |
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V |
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4.5V |
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0 |
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0.1 |
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0.1 |
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0.1 |
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V |
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6.0V |
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0 |
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0.1 |
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0.1 |
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0.1 |
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V |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
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4.5V |
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0.2 |
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0.26 |
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0.33 |
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0.4 |
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V |
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|IOUT| ≤ 5.2 mA |
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6.0V |
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0.2 |
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0.26 |
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0.33 |
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0.4 |
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V |
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IIN |
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Maximum Input |
VIN = VCC or GND |
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6.0V |
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±0.1 |
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±1.0 |
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±1.0 |
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μA |
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Current |
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ICC |
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Maximum Quiescent |
VIN = VCC or GND |
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6.0V |
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8.0 |
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80 |
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160 |
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μA |
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Supply Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when |
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designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur- |
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rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. |
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3 |
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