Fairchild Semiconductor MM74HC4060SJX, MM74HC4060N, MM74HC4060M, MM74HC4060SJ, MM74HC4060MX Datasheet
...
August 1984
Revised February 1999
MM74HC4060
14 Stage Binary Counter
General Description
The MM74HC4060 is a high speed binary ripple carry counter. These counters are implemented utilizing advanced silicon-gate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low power and high noise immunity of CMOS.
The MM74HC4060 is a 14-stage counter, which device increments on the falling edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input. The MM74HC4060 also has two additional inputs to enable easy connection of either an RC or crystal oscillator.
This device is pin equivalent to the CD4060. All inputs are protected from damage due to static discharge by protection diodes to VCC and ground.
Features
■Typical propagation delay: 16 ns
■Wide operating voltage range: 2–6V
■Low input current: 1 μA maximum
■Low quiescent current: 80 μA maximum (74 Series)
■Output drive capability: 10 LS-TTL loads
Ordering Code:
Order Number |
Package Number |
Package Description |
|
|
|
MM74HC4060M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
|
|
|
MM74HC4060SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
|
|
|
MM74HC4060MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
|
|
|
MM74HC4060N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
|
|
|
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Counter Binary Stage 14 MM74HC4060
© 1999 Fairchild Semiconductor Corporation |
DS005354.prf |
www.fairchildsemi.com |
MM74HC4060
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
|
Supply Voltage (VCC) |
−0.5 to +7.0V |
DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Clamp Diode Current (ICD) |
±20 mA |
DC Output Current, per pin (IOUT) |
±25 mA |
DC VCC or GND Current, per pin (ICC) |
±50 mA |
Storage Temperature Range (TSTG) |
−65°C to +150°C |
Power Dissipation (PD) |
|
(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
260°C |
(Soldering 10 seconds) |
Recommended Operating
Conditions
|
Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
|
|
|
(VIN, VOUT) |
0 |
VCC |
V |
Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise or Fall Times |
|
|
|
(tr, tf) VCC = 2.0V |
|
1000 |
ns |
VCC = 4.5V |
|
500 |
ns |
VCC = 6.0V |
|
400 |
ns |
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating: plastic “N” package: −12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol |
Parameter |
Conditions |
VCC |
TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
||
Typ |
|
Guaranteed Limits |
|||||||
|
|
|
|
|
|
|
|
|
|
VIH |
Minimum HIGH |
|
2.0V |
|
1.5 |
1.5 |
1.5 |
V |
|
|
Level Voltage |
|
4.5V |
|
3.15 |
3.15 |
3.15 |
V |
|
|
(Not Applicable to Pins 9 & 10) |
|
6.0V |
|
4.2 |
4.2 |
4.2 |
V |
|
|
|
|
|
|
|
|
|
|
|
VIL |
Maximum LOW Level |
|
2.0V |
|
0.5 |
0.5 |
0.5 |
V |
|
|
Input Voltage |
|
4.5V |
|
1.35 |
1.35 |
1.35 |
V |
|
|
(Not Applicable to Pins 9 & 10) |
|
6.0V |
|
1.8 |
1.8 |
1.8 |
V |
|
|
|
|
|
|
|
|
|
|
|
VOH |
Minimum HIGH Level |
VIN = VIH or VIL |
|
|
|
|
|
|
|
|
Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
|
|
|
|
|
4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
|
|
|
|
6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
|
|
|
|
|
|
|
|
|
|
|
|
Except Pins |
VIN = VIH or VIL |
|
|
|
|
|
|
|
|
9 & 10 |
|IOUT| ≤ 4.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
|
|
|
|IOUT| ≤ 5.2 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
|
|
Pins |
VIN = VIH or VIL |
|
|
3.98 |
3.84 |
3.7 |
V |
|
|
9 & 10 |
|IOUT| = 0.4 mA |
|
|
5.48 |
5.34 |
5.2 |
V |
|
|
|
|IOUT| = 0.52 mA |
|
|
|
|
|
|
VOL |
Maximum LOW Level |
VIN = VIH or VIL |
|
|
|
|
|
|
|
|
Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
|
|
|
|
|
4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
|
|
|
|
6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
|
|
|
|
|
|
|
|
|
|
|
|
Except Pins |
VIN = VIH or VIL |
|
|
|
|
|
|
|
|
9 & 10 |
|IOUT| ≤ 4.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
|
|
|
|IOUT| ≤ 5.2 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
|
|
Pins |
VIN = VIH or VIL |
|
|
0.26 |
0.33 |
0.4 |
V |
|
|
9 & 10 |
|IOUT| = 0.4 mA |
|
|
0.26 |
0.33 |
0.4 |
V |
|
|
|
|IOUT| = 0.52 mA |
|
|
|
|
|
|
IIN |
Maximum Input Current |
VIN = VCC or GND |
6.0V |
|
±0.1 |
±1.0 |
±1.0 |
μA |
|
ICC |
Maximum Quiescent |
VIN = VCCor GND |
|
|
|
|
|
|
|
|
Supply Current |
IOUT = 0 μA |
6.0V |
|
8.0 |
80 |
160 |
μA |
|
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
MM74HC4060
3 |
www.fairchildsemi.com |
Loading...