September 1983
Revised February 1999
MM74HC139 Dual 2-To-4 Line Decoder
© 1999 Fairchild Semiconductor Corporation DS005311.prf www.fairchildsemi.com
MM74HC139
Dual 2-To-4 Line Decoder
General Description
The MM74HC139 decoder utilizes advanced silicon-gate
CMOS technology, and is well suite d to memory address
decoding or data routing applications. It possesses the
high noise immunity and l ow power consumption usually
associated with CMOS circuitry, yet has speeds compar a-
ble to low power Schottky TTL logic.
The MM74HC139 contain two independent one-of-four
decoders each with a single active low enable input (G1, or
G2). Data on the select inputs (A 1, and B1 or A2, an d B2)
cause one of the four normally high outputs to go LOW.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent lo ads, and are functionally a s well as pin
equivalent to the 74LS 139. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
■ Typical propagation delays —
Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
■ Low power: 40 µW quiescent s upply power
■ Fanout of 10 LS-TTL devices
■ Input current maximum 1 µA, typical 10 pA
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram
Pin Assignments f or DIP, SOIC, SOP and TSSOP
Truth Table
H = HIGH Level
L = LOW Level
X = Don't Care
Order Number Package Number Package Description
MM74HC139M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC139MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP) JEDEC MO-153, 4.4mm Wide
MM74HC139N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Outputs
Enable Select
G B A Y0Y1Y2Y3
H XXHHHH
LLLLHHH
LLHHLHH
LHLHHLH
L HHHHHL