February 1984
Revised February 1999
MM74HCT138
3-to-8 Line Decoder
General Description
The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits feature high noise immunity and low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.
The MM74HCT138 have 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading decoders.
The decoders’ output can drive 10 low power Schottky TTL equivalent loads and are functionally and pin equivalent to
the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
Features
■TTL input compatible
■Typical propagation delay: 20 ns
■Low quiescent current: 80 μA maximum (74HCT Series)
■Low input current: 1 μA maximum
■Fanout of 10 LS-TTL loads
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HCT138M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
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MM74HCT138SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HCT138MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HCT138N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Decoder Line 8-to-3 MM74HCT138
© 1999 Fairchild Semiconductor Corporation |
DS005362.prf |
www.fairchildsemi.com |
MM74HCT138
Truth Table
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Inputs |
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Outputs |
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Enable |
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Select |
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G1 |
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C B A |
Y0 |
Y1 |
Y2 Y3 Y4 Y5 Y6 Y7 |
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G2 |
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(Note 1) |
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X |
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H |
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X X X |
H H H H H H H H |
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L |
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X |
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X X X |
H |
H H H H H H H |
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H |
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L |
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L L L |
L H |
H H H H H H |
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H |
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L |
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L L H |
H L H H H H H H |
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H |
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L |
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L H L |
H H L H H H H H |
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H |
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L |
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L H H |
H H H L H H H H |
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H |
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L |
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H L L |
H H H H L H H H |
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H |
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L |
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H L H |
H H H H H L H H |
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H |
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L |
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H H L |
H H H H H H L H |
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H |
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L |
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H H H |
H H H H H H H L |
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H = HIGH Level
L = LOW Level
X = Don’t Care
Note 1: G2 = G2A + G2B
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 2) |
Recommended Operating |
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MM74HCT138 |
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(Note 3) |
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Conditions |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
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Min |
Max |
Units |
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DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
Supply Voltage (V |
CC |
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4.5 |
5.5 |
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V |
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DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
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DC Input or Output Voltage |
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Clamp Diode Current (IIK, IOK) |
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±20 mA |
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(V |
IN |
, V |
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0 |
V |
CC |
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V |
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DC Output Current, per pin (IOUT) |
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±25 mA |
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OUT |
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Operating Temperature Range (TA) |
−40 |
+85 |
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°C |
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DC VCC or GND Current, per pin (ICC) |
±50 mA |
Input Rise or Fall Times |
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Storage Temperature Range (TSTG) |
−65°C to +150°C |
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(t , t ) |
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500 |
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ns |
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Power Dissipation (PD) |
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r |
f |
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Note 2: Absolute Maximum Ratings are those values beyond which dam- |
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(Note 4) |
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600 mW |
age to the device may occur. |
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Note 3: Unless otherwise specified all voltages are referenced to ground. |
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S.O. Package only |
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500 mW |
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Note 4: Power Dissipation temperature derating — plastic “N” package: − |
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Lead Temperature (TL) |
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260°C |
12 mW/°C from 65°C to 85°C. |
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(Soldering 10 seconds) |
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DC Electrical Characteristics |
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VCC = 5V ±10% (unless otherwise specified) |
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Symbol |
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Parameter |
Conditions |
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TA = 25°C |
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TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
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Minimum HIGH Level |
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2.0 |
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2.0 |
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2.0 |
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V |
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Input Voltage |
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VIL |
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Maximum LOW Level |
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0.8 |
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0.8 |
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0.8 |
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V |
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Input Voltage |
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VOH |
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Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| = 20 μA |
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VCC |
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VCC− 0.1 |
VCC− 0.1 |
VCC− 0.1 |
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V |
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|IOUT| = 4.0 mA, VCC = 4.5V |
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4.2 |
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3.98 |
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3.84 |
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3.7 |
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V |
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|IOUT| = 4.8 mA, VCC = 5.5V |
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5.2 |
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4.98 |
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4.84 |
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4.7 |
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V |
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VOL |
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Maximum LOW Level |
VIN = VIH or VIL |
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Voltage |
|IOUT| = 20 μA |
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0 |
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0.1 |
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0.1 |
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0.1 |
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V |
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|IOUT| = 4.0 mA, VCC = 4.5V |
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0.2 |
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0.26 |
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0.33 |
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0.4 |
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V |
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|IOUT| = 4.8 mA, VCC = 5.5V |
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0.2 |
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0.26 |
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0.33 |
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0.4 |
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V |
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IIN |
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Maximum Input |
VIN = VCC or GND, |
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±0.1 |
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±1.0 |
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±1.0 |
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μA |
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Current |
VIH or VIL |
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ICC |
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Maximum Quiescent |
VIN = VCC or GND |
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8.0 |
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80 |
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160 |
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μA |
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Supply Current |
IOUT = 0 μA |
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VIN = 2.4V or 0.5V (Note 5) |
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0.3 |
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0.4 |
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0.5 |
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mA |
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Note 5: This is measured per input pin. All other inputs are held at VCC or ground. |
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3 |
www.fairchildsemi.com |