February 1984
Revised October 1999
MM74HC4049 • MM74HC4050
Hex Inverting Logic Level Down Converter •
Hex Logic Level Down Converter
General Description
The MM74HC4049 and the MM74HC4050 utilize advanced silicon-gate CMOS technology, and have a modified input protection structure that enables these parts to be used as logic level translators which will convert high level logic to a low level logic while operating from the low logic supply. For example, 0–15V CMOS logic can be converted to 0–5V logic when using a 5V supply. The modified input protection has no diode connected to VCC, thus allowing the input voltage to exceed the supply. The lower zener diode protects the input from both positive and negative static voltages. In addition each part can be used as a sim-
ple buffer or inverter without level translation. The MM74HC4049 is pin and functionally compatible to the CD4049BC and the MM74HC4050 is compatible to the CD4050BC
Features
■Typical propagation delay: 8 ns
■Wide power supply range: 2V–6V
■Low quiescent supply current: 20 μA maximum (74HC)
■Fanout of 10 LS-TTL loads
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC4049M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
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MM74HC4049SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC4049MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide |
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MM74HC4049N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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MM74HC4050M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
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MM74HC4050SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC4050MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide |
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MM74HC4050N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
MM74HC4049 |
MM74HC4050 |
Converter Down Level Logic Hex • Converter Down Level Logic Inverting Hex MM74HC4050 • MM74HC4049
© 1999 Fairchild Semiconductor Corporation |
DS005214 |
www.fairchildsemi.com |
MM74HC4049 • MM74HC4050
Absolute Maximum Ratings(Note 1)
(Note 2) |
|
Supply Voltage (VCC) |
−0.5 to +7.0V |
DC Input Voltage (VIN) |
−1.5 to +18V |
DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Clamp Diode Current (IZK, IOK) |
−20 mA |
DC Output Current, per pin (IOUT) |
±25 mA |
DC VCC or GND Current, per pin (ICC) |
±50 mA |
Storage Temperature Range (TSTG) |
−65°C to +150°C |
Power Dissipation (PD) |
|
(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
|
(Soldering 10 seconds) |
260°C |
Recommended Operating
Conditions
|
Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input Voltage |
0 |
15 |
V |
(VIN) |
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|
DC Output Voltage |
0 |
VCC |
V |
(VOUT) |
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Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise or Fall Times |
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(tr, tf) VCC = 2.0V |
|
1000 |
ns |
VCC = 4.5V |
|
500 |
ns |
VCC = 6.0V |
|
400 |
ns |
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics |
(Note 4) |
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Symbol |
Parameter |
Conditions |
VCC |
TA = 25°C |
TA = −40°C to 85°C |
TA = −55°C to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level Input |
|
2.0V |
|
1.5 |
1.5 |
1.5 |
V |
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Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
V |
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VIL |
Maximum LOW Level Input |
|
2.0V |
|
0.5 |
0.5 |
0.5 |
V |
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Voltage |
|
4.5V |
|
1.35 |
1.35 |
1.35 |
V |
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6.0V |
|
1.8 |
1.8 |
1.8 |
V |
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VOH |
Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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|IOUT| ≤ 5.2 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
|
VOL |
Maximum LOW Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 4 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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|IOUT| ≤ 5.2 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
|
IIN |
Maximum Input Current |
VIN = VCC or GND |
6.0V |
|
±0.1 |
±1.0 |
±1.0 |
μA |
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|
VIN = 15V |
2.0V |
|
±0.5 |
±5 |
±5 |
μA |
|
ICC |
Maximum Quiescent Supply |
VIN = VCC or GND |
6.0V |
|
2.0 |
20 |
40 |
μA |
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Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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