Fairchild Semiconductor MM74HC573WM, MM74HC573WMX, MM74HC573SJ, MM74HC573MTC, MM74HC573MTCX Datasheet

September 1983

Revised May 2000

MM74HC573

3-STATE Octal D-Type Latch

General Description

The MM74HC573 high speed octal D-type latches utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system.

When the LATCH ENABLE(LE) input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a HIGH logic level is applied to the OUTPUT CONTROL OC input, all outputs go to a HIGH impedance state, regardless

of what signals are present at the other inputs and the state of the storage elements.

The 74HC logic family is speed, function and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

■Typical propagation delay: 18 ns

■Wide operating voltage range: 2 to 6 volts

■Low input current: 1 A maximum

■Low quiescent current: 80 A maximum (74HC Series)

■Compatible with bus-oriented systems

■Output drive capability: 15 LS-TTL loads

Ordering Code:

Order Number	Package Number	Package Description
MM74HC573WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MM74HC573SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC573MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC573N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Truth Table
			Output		Latch	Data	Output
			Control		Enable
			L		H	H	H
			L		H	L	L
			L		L	X	Q0
			H		X	X	Z
	H
		= HIGH Level
	L =		LOW Level
	Q0 = Level of output before steady-state input conditions were established.
	Z =		High Impedance
	X =		Don't Care

Top View

Latch Type-D Octal STATE-3 MM74HC573

© 2000 Fairchild Semiconductor Corporation

DS005212

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MM74HC573

Absolute Maximum Ratings(Note 1)

(Note 2)
Supply Voltage (VCC)	− 0.5 to + 7.0V
DC Input Voltage (VIN)	− 1.5 to VCC + 1.5V
DC Output Voltage (VOUT)	− 0.5 to VCC + 0.5V
Clamp Diode Current (IIK, IOK)	± 20 mA
DC Output Current, per pin (IOUT)	± 35 mA
DC VCC or GND Current, per pin (ICC)	± 70 mA
Storage Temperature Range (TSTG)	− 65° C to + 150° C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)
(Soldering 10 seconds)	260° C

Recommended Operating

Conditions

		Min	Max	Units
Supply Voltage (VCC)		2	6	V
DC Input or Output Voltage		0	VCC	V
(VIN, VOUT)
Operating Temperature Range (TA)		− 40	+ 85	° C
Input Rise or Fall Times
(tr, tf) VCC =	2.0V		1000	ns
VCC =	4.5V		500	ns
VCC =	6.0V		400	ns

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/° C from 65° C to 85° C.

DC Electrical Characteristics (Note 4)

Symbol	Parameter	Conditions			VCC	TA =	25° C	TA = − 40 to 85° C	TA =	− 55 to 125° C	Units
						Typ		Guaranteed Limits
VIH	Minimum HIGH Level Input				2.0V		1.5	1.5		1.5	V
	Voltage				4.5V		3.15	3.15		3.15	V
					6.0V		4.2	4.2		4.2	V
VIL	Maximum LOW Level Input				2.0V		0.5	0.5		0.5	V
	Voltage				4.5V		1.35	1.35		1.35	V
					6.0V		1.8	1.8		1.8	V
VOH	Minimum HIGH Level Output	VIN =	VIH or VIL
	Voltage	|IOUT| ≤		20 µ A	2.0V	2.0	1.9	1.9		1.9	V
					4.5V	4.5	4.4	4.4		4.4	V
					6.0V	6.0	5.9	5.9		5.9	V
		VIN = VIH or VIL
		|IOUT| ≤		6.0 mA	4.5V	4.2	3.98	3.84		3.7	V
		|IOUT| ≤		7.8 mA	6.0V	5.7	5.48	5.34		5.2	V
VOL	Maximum LOW Level Output	VIN =	VIH or VIL
	Voltage	|IOUT| ≤		20 µ A	2.0V	0	0.1	0.1		0.1	V
					4.5V	0	0.1	0.1		0.1	V
					6.0V	0	0.1	0.1		0.1	V
		VIN = VIH or VIL
		|IOUT| ≤		6.0 mA	4.5V	0.2	0.26	0.33		0.4	V
		|IOUT| ≤		7.8 mA	6.0V	0.2	0.26	0.33		0.4	V
IIN	Maximum Input Current	VIN =	VCC or GND		6.0V		± 0.1	± 1.0		± 1.0	µ A
IOZ	Maximum 3-STATE Output	VOUT =		VCC or GND
	Leakage Current	OC =	VIH		6.0V		± 0.5	± 5.0		± 10	µ A
ICC	Maximum Quiescent Supply	VIN =	VCC or GND
	Current	IOUT =		0 µ A	6.0V		8.0	80		160	µ A
∆ ICC	Quiescent Supply Current	VCC =	5.5V		OE	1.0	1.5	1.8		2.0	mA
	per Input Pin	VIN =	2.4V		LE	0.6	0.8	1.0		1.1	mA
		or 0.4V (Note 4)			DATA	0.4	0.5	0.6		0.7	mA

Note 4: For a power supply of 5V ± 10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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AC Electrical Characteristics

VCC = 5V, TA = 25° C, tr = tf = 6 ns

Symbol	Parameter		Conditions	Typ	Guaranteed	Units
					Limit
tPHL, tPLH	Maximum Propagation Delay, Data to Q	CL =	45 pF	16	20	ns
tPHL, tPLH	Maximum Propagation Delay, LE to Q	CL =	45 pF	14	22	ns
tPZH, tPZL	Maximum Output Enable Time	RL =	1 kΩ	15	27	ns
		CL =	45 pF
tPHZ, tPLZ	Maximum Output Disable Time	RL =	1 kΩ	13	23	ns
		CL =	5 pF
tS	Minimum Set Up Time, Data to LE			10	15	ns
tH	Minimum Hold Time, LE to Data			2	5	ns
tW	Minimum Pulse Width, LE or Data			10	16	ns

AC Electrical Characteristics

Symbol	Parameter		Conditions		VCC	TA =	25° C	TA = − 40 to 85° C	TA =	− 55 to 125° C	Units
						Typ		Guaranteed Limits
tPHL, tPLH	Maximum Propagation		CL =	50 pF	2.0V	45	110	138		165	ns
	Delay Data to Q		CL =	150 pF	2.0V	58	150	188		225	ns
			CL =	50 pF	4.5V	17	22	28		33	ns
			CL =	150 pF	4.5V	21	30	38		40	ns
			CL =	50 pF	6.0V	15	19	24		29	ns
			CL =	150 pF	6.0V	19	26	33		39	ns
tPHL, tPLH	Maximum Propagation		CL =	50 pF	2.0V	46	115	138		165	ns
	Delay, LE to Q		CL =	150 pF	2.0V	60	155	194		233	ns
			CL =	50 pF	4.5V	14	23	29		35	ns
			CL =	150 pF	4.5V	21	31	47		47	ns
			CL =	50 pF	6.0V	12	20	25		30	ns
			CL =	150 pF	6.0V	19	27	34		41	ns
tPZH, tPZL	Maximum Output Enable		RL =	1 kΩ
	Time		CL =	50 pF	2.0V	55	140	175		210	ns
			CL =	150 pF	2.0V	67	180	225		270	ns
			CL =	50 pF	4.5V	15	28	35		42	ns
			CL =	150 pF	4.5V	24	36	45		54	ns
			CL =	50 pF	6.0V	14	24	30		36	ns
			CL =	150 pF	6.0V	22	31	39		47	ns
tPHZ, tPLZ	Maximum Output Disable		RL =	1 kΩ	2.0V	40	125	156		188	ns
	Time		CL =	50 pF	4.5V	13	25	31		38	ns
					6.0V	12	21	27		32	ns
tS	Minimum Set Up Time				2.0V	30	75	95		110	ns
	Data to LE				4.5V	10	15	19		22	ns
					6.0V	9	13	16		19	ns
tH	Minimum Hold Time				2.0V		25	31		38	ns
	LE to Data				4.5V		5	6		7	ns
					6.0V		4	5		6	ns
tW	Minimum Pulse Width LE,				2.0V	30	80	100		120	ns
	or Data				4.5V	9	16	20		24	ns
					6.0V	8	14	18		20	ns
tTLH, tTHL	Maximum Output Rise		CL =	50 pF	2.0V	25	60	75		90	ns
	and Fall Time, Clock				4.5V	7	12	15		18	ns
					6.0V	6	10	13		15	ns
CPD	Power Dissipation Capacitance		OC =	VCC		5					pF
	(Note 5) (per latch)		OC =	GND		52					pF
CIN	Maximum Input					5	10	10		10	pF
	Capacitance

MM74HC573

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