Fairchild Semiconductor MM74HC165MTC, MM74HC165MTCX, MM74HC165MX, MM74HC165N, MM74HC165SJX Datasheet

September 1983

Revised February 1999

MM74HC165

Parallel-in/Serial-out 8-Bit Shift Register

General Description

The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology. It has the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads.

This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input. Also included is a gated CLOCK input and a complementary output from the eighth bit.

Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function. Holding either of the CLOCK inputs high inhibits clocking, and holding either CLOCK input low with the SHIFT/LOAD input high enables the other CLOCK input. Data transfer occurs on the positive going edge of the clock. Parallel

loading is inhibited as long as the SHIFT/LOAD input is HIGH. When taken LOW, data at the parallel inputs is loaded directly into the register independent of the state of the clock.

The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

■Typical propagation delay: 20 ns (clock to Q)

■Wide operating supply voltage range: 2–6V

■Low input current: 1 μA maximum

■Low quiescent supply current: 80 μA maximum (74HC Series)

■Fanout of 10 LS-TTL loads

Ordering Code:

Order Number	Package Number	Package Description
MM74HC165M	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC165SJ	M16D	16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC165MTC	MTC16	16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC165	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Function Table

		Inputs			Internal		Output
							QH
Shift/	Clock	Clock	Serial	Parallel	Outputs
Load	Inhibit			A. . .H	QA	QB
L	X	X	X	a. . .h a		b	h
H	L	L	X	X	QA0 QB0		QH0
H	L	−	H	X	H	QAN	QGN
H	L	−	L	X	L	QAN	QGN
H	H	X	X	X QA0 QB0			QH0

H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelevant (any input, including transitions)

− = Transition from LOW-to-HIGH level

QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established.

QAN, QGN = The level of QA or QG before the most recent − transition of the clock; indicates a one-bit shift.

Top View

Register Shift Bit-8 out-in/Serial-Parallel MM74HC165

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MM74HC165

Logic Diagrams

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Absolute Maximum Ratings(Note 1)

(Note 2)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC +1.5V
DC Output Voltage (VOUT)	−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)	±20 mA
DC Output Current, per pin (IOUT)	±25 mA
DC VCC or GND Current, per pin (ICC)	±50 mA
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	2	6	V
DC Input or Output Voltage
(VIN, VOUT)	0	VCC	V
Operating Temperature Range (TA)	−40	+85	°C
Input Rise or Fall Times
(tr, tf) VCC = 2.0V		1000	ns
VCC = 4.5V		500	ns
VCC = 6.0V		400	ns

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Symbol	Parameter	Conditions	VCC	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
				Typ		Guaranteed Limits
VIH	Minimum HIGH Level		2.0V		1.5	1.5	1.5	V
	Input Voltage		4.5V		3.15	3.15	3.15	V
			6.0V		4.2	4.2	4.2	V
VIL	Maximum LOW Level		2.0V		0.5	0.5	0.5	V
	Input Voltage		4.5V		1.35	1.35	1.35	V
			6.0V		1.8	1.8	1.8	V
VOH	Minimum HIGH Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	2.0	1.9	1.9	1.9	V
			4.5V	4.5	4.4	4.4	4.4	V
			6.0V	6.0	5.9	5.9	5.9	V
		VIN = VIH or VIL
		|IOUT| ≤ 4.0 mA	4.5V	4.2	3.98	3.84	3.7	V
		|IOUT| ≤ 5.2 mA	6.0V	5.7	5.48	5.34	5.2	V
VOL	Maximum LOW Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	0	0.1	0.1	0.1	V
			4.5V	0	0.1	0.1	0.1	V
			6.0V	0	0.1	0.1	0.1	V
		VIN = VIH or VIL
		|IOUT| ≤ 4.0 mA	4.5V	0.2	0.26	0.33	0.4	V
		|IOUT| ≤ 5.2 mA	6.0V	0.2	0.26	0.33	0.4	V
IIN	Maximum Input	VIN = VCC or GND	6.0V		±0.1	±1.0	±1.0	μA
	Current	VCC = 2−6V
ICC	Maximum Quiescent	VIN = VCC or GND	6.0V		8.0	80	160	μA
	Supply Current	IOUT = 0 μA
		VCC = 2−6V

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

MM74HC165

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