Fairchild Semiconductor MM74HC595WMX, MM74HC595SJX, MM74HC595SJ, MM74HC595MTCX, MM74HC595CW Datasheet

September 1983

Revised February 1999

MM74HC595

8-Bit Shift Registers with Output Latches

General Description

The MM74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.

The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

■Low quiescent current: 80 μA maximum (74HC Series)

■Low input current: 1 μA maximum

■8-bit serial-in, parallel-out shift register with storage

■Wide operating voltage range: 2V–6V

■Cascadable

■Shift register has direct clear

■Guaranteed shift frequency: DC to 30 MHz

Ordering Code:

Order Number	Package Number	Package Description
MM74HC595M	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC595WM	M16B	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC595SJ	M16D	16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC595MTC	MTC16	16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC595N	N16E	16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP		RCK	SCK		SCLR			G		Function
		X	X		X			H		QA thru QH = 3-STATE
		X	X		L			L		Shift Register cleared
										QH = 0
		X	−		H			L		Shift Register clocked
										QN = Qn-1, Q0 = SER
		−	X		H			L		Contents of Shift
										Register transferred
										to output latches
Top View

Latches Output with Registers Shift Bit-8 MM74HC595

© 1999 Fairchild Semiconductor Corporation

DS005342.prf

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MM74HC595

Logic Diagram

(positive logic)

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2

Absolute Maximum Ratings(Note 1)

(Note 2)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC +1.5V
DC Output Voltage (VOUT)	−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)	±20 mA
DC Output Current, per pin (IOUT)	±35 mA
DC VCC or GND Current,	±70 mA
per pin (ICC)
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

DC Electrical Characteristics (Note 4)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	2	6	V
DC Input or Output Voltage
(VIN, VOUT)	0	VCC	V
Operating Temperature Range (TA)	−40	+85	°C
Input Rise or Fall Times
(tr, tf) VCC = 2.0V		1000	ns
VCC = 4.5V		500	ns
VCC = 6.0V		400	ns

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

Symbol	Parameter		Conditions	VCC	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
					Typ		Guaranteed Limits
VIH	Minimum HIGH Level			2.0V		1.5	1.5	1.5	V
	Input Voltage			4.5V		3.15	3.15	3.15	V
				6.0V		4.2	4.2	4.2	V
VIL	Maximum LOW Level			2.0V		0.5	0.5	0.5	V
	Input Voltage			4.5V		1.35	1.35	1.35	V
				6.0V		1.8	1.8	1.8	V
VOH	Minimum HIGH Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA		2.0V	2.0	1.9	1.9	1.9	V
				4.5V	4.5	4.4	4.4	4.4	V
				6.0V	6.0	5.9	5.9	5.9	V
	QH	VIN = VIH or VIL
		|IOUT| ≤ 4.0 mA		4.5V	4.2	3.98	3.84	3.7	V
		|IOUT| ≤ 5.2 mA		6.0V	5.2	5.48	5.34	5.2	V
	QA thru QH	VIN = VIH or VIL
		|IOUT| ≤ 6.0 mA		4.5V	4.2	3.98	3.84	3.7	V
		|IOUT| ≤ 7.8 mA		6.0V	5.7	5.48	5.34	5.2	V
VOL	Maximum LOW Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA		2.0V	0	0.1	0.1	0.1	V
				4.5V	0	0.1	0.1	0.1	V
				6.0V	0	0.1	0.1	0.1	V
	QH	VIN = VIH or VIL
		|IOUT| ≤ 4 mA		4.5V	0.2	0.26	0.33	0.4	V
		|IOUT| ≤ 5.2 mA		6.0V	0.2	0.26	0.33	0.4	V
	QA thru QH	VIN = VIH or VIL
		|IOUT| ≤ 6.0 mA		4.5V	0.2	0.26	0.33	0.4	V
		|IOUT| ≤ 7.8 mA		6.0V	0.2	0.26	0.33	0.4	V
IIN	Maximum Input	VIN = VCC or GND		6.0V		±0.1	±1.0	±1.0	μA
	Current
IOZ	Maximum 3-STATE	VOUT = VCC or GND		6.0V		±0.5	±5.0	±10	μA
	Output Leakage		= VIH
		G
ICC	Maximum Quiescent	VIN = VCC or GND		6.0V		8.0	80	160	μA
	Supply Current	IOUT = 0 μA

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

MM74HC595

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