February 1984
Revised February 2000
MM74HC4514
4-to-16 Line Decoder with Latch
General Description
The MM74HC4514 utilizes advanced silicon-gate CMOS technology, which is well suited to memory address decoding or data routing application. It possesses high noise immunity and low power dissipation usually associated with CMOS circuitry, yet speeds comparable to low power Schottky TTL circuits. It can drive up to 10 LS-TTL loads.
The MM74HC4514 contain a 4-to-16 line decoder and a 4- bit latch. The latch can store the data on the select inputs, thus allowing a selected output to remain HIGH even though the select data has changed. When the LATCH ENABLE input to the latches is HIGH the outputs will change with the inputs. When LATCH ENABLE goes LOW the data on the select inputs is stored in the latches. The four select inputs determine which output will go HIGH provided the INHIBIT input is LOW. If the INHIBIT input is HIGH all outputs are held LOW thus disabling the decoder.
The MM74HC4514 is functionally and pinout equivalent to the CD4514BC and the MC1451BC. All inputs are protected against damage due to static discharge diodes from VCC and ground.
Features
■Typical propagation delay: 18 ns
■Low quiescent power: 80 μA maximum (74HC Series)
■Low input current: 1 μA maximum
■Fanout of 10 LS-TTL loads (74HC Series)
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC4514WM |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-0013, 0.300” Wide |
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MM74HC4514MTC |
MTC24 |
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC4514N |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Latch with Decoder Line 16-to-4 MM74HC4514
© 2000 Fairchild Semiconductor Corporation |
DS005215 |
www.fairchildsemi.com |
MM74HC4514
Connection Diagram
Top View
Logic Diagram
Truth Table
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Data Inputs |
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LE |
Inhibit |
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Selected |
D |
C |
B |
A |
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Output |
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High |
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H |
L |
L |
L |
L |
L |
S0 |
H |
L |
L |
L |
L |
H |
S1 |
H |
L |
L |
L |
H |
L |
S2 |
H |
L |
L |
L |
H |
H |
S3 |
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H |
L |
L |
H |
L |
L |
S4 |
H |
L |
L |
H |
L |
H |
S5 |
H |
L |
L |
H |
H |
L |
S6 |
H |
L |
L |
H |
H |
H |
S7 |
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H |
L |
H |
L |
L |
L |
S8 |
H |
L |
H |
L |
L |
H |
S9 |
H |
L |
H |
L |
H |
L |
S10 |
H |
L |
H |
L |
H |
H |
S11 |
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H |
L |
H |
H |
L |
L |
S12 |
H |
L |
H |
H |
L |
H |
S13 |
H |
L |
H |
H |
H |
L |
S14 |
H |
L |
H |
H |
H |
H |
S15 |
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All |
X |
H |
X |
X |
X |
X |
Outputs = 0 |
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Latched |
L |
L |
X |
X |
X |
X |
Data |
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www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Clamp Diode Current (IIK, IOK) |
±20 mA |
DC Output Current, per pin (IOUT) |
±25 mA |
DC VCC or GND Current, per pin (ICC) |
±50 mA |
Storage Temperature Range (TSTG) |
−65°C to +150°C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
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(Soldering 10 seconds) |
260°C |
Recommended Operating
Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
0 |
VCC |
V |
(VIN, VOUT) |
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Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise or Fall Times |
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(tr, tf) VCC = 2.0V |
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1000 |
ns |
VCC = 4.5V |
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500 |
ns |
VCC = 6.0V |
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400 |
ns |
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics |
(Note 4) |
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Symbol |
Parameter |
Conditions |
VCC |
TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
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2.0V |
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1.5 |
1.5 |
1.5 |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
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VIL |
Maximum LOW Level |
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2.0V |
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0.5 |
0.5 |
0.5 |
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Input Voltage |
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4.5V |
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1.35 |
1.35 |
1.35 |
V |
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6.0V |
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1.8 |
1.8 |
1.8 |
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VOH |
Minimum HIGH Level |
VIN = VIH or VIL |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
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Output Voltage |
|IOUT| ≤ 20 μA |
4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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|IOUT| ≤ 5.2 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
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VOL |
Maximum LOW Level |
VIN = VIH or VIL |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
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Output Voltage |
|IOUT| ≤ 20 μA |
4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
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VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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|IOUT| ≤ 5.2 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
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IIN |
Maximum Input Current |
VIN = VCC or GND |
6.0V |
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±0.1 |
±1.0 |
±1.0 |
μA |
ICC |
Maximum Quiescent |
VIN = VCC or GND |
6.0V |
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8.0 |
80 |
160 |
μA |
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Supply Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
MM74HC4514
3 |
www.fairchildsemi.com |
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