September 1983
Revised February 1999
MM74HC154 4-to-16 Line Decoder
© 1999 Fairchild Semiconductor Corporation DS005122.prf www.fairchildsemi.com
MM74HC154
4-to-16 Line Decoder
General Description
The MM74HC154 decoder utilizes advanced silicon-gate
CMOS technology, and is well suite d to memory address
decoding or data routing applications. It posse sses high
noise immunity, and low power consumption of CMOS with
speeds similar to low power Schottky TTL circuits.
The MM74HC154 have 4 binary select inputs (A, B, C, and
D). If the device is e nabled these inputs de termine which
one of the 16 normally HIGH outputs will go LOW. Two
active LOW enables (G1
and G2) are provided to ease
cascading of decoders with little or no external logic.
Each output can drive 10 low p ower Schottk y TTL eq uiva-
lent loads, and is functionally and pin equivalent to the
74LS154. All inputs are protected from damage due to
static discharge by diodes to V
CC
and ground.
Features
■ Typical propagation delay: 21 ns
■ Power supp ly quiescent current: 80 µA
■ Wide power supply voltage range: 2–6V
■ Low input current: 1 µA maximum
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram
Pin Assignments for DIP, SOIC and TSSOP
Top View
Truth Table
Note 1: All others HIGH
Order Number Package Number Package Description
MM74HC154WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
MM74HC154MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC154N N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Inputs Low
G1
G2 DCBAOutput
(Note 1)
LLLLLL 0
LLLLLH 1
LLLLHL 2
LLLLHH 3
LLLHLL 4
LLLHLH 5
LLLHHL 6
LLLHHH 7
LLHLLL 8
LLHLLH 9
LLHLHL 10
LLHLHH 11
LLHHLL 12
LLHHLH 13
LLHHHL 14
LLHHHH 15
LHXXXX —
HLXXXX —
HHXXXX —