September 1983
Revised August 2000
MM74HC240
Inverting Octal 3-STATE Buffer
General Description
The MM74HC240 3-STATE buffer utilizes advanced sili- con-gate CMOS technology. It possesses high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity and low power consumption. It has a fanout of 15 LS-TTL equivalent inputs.
The MM74HC240 is an inverting buffer and has two active LOW enables (1G and 2G). Each enable independently controls 4 buffers.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
■Typical propagation delay: 12 ns
■3-STATE outputs for connection to system buses
■Wide power supply range: 2–6V
■Low quiescent supply current: 80 A (74 Series)
■Output current: 6 mA
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC240WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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MM74HC240SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC240MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC240N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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1G |
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1A |
1Y |
2G |
2A |
2Y |
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L |
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L |
H |
L |
L |
H |
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L |
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H |
L |
L |
H |
L |
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H |
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L |
Z |
H |
L |
Z |
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H |
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H |
Z |
H |
H |
Z |
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H = HIGH Level |
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L = LOW Level |
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Z = HIGH Impedance |
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Top View |
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Buffer STATE-3 Octal Inverting MM74HC240
© 2000 Fairchild Semiconductor Corporation |
DS005020 |
www.fairchildsemi.com |
MM74HC240
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
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Supply Voltage (VCC) |
− 0.5 to + 7.0V |
DC Input Voltage (VIN) |
− 1.5 to VCC + 1.5V |
DC Output Voltage (VOUT) |
− 0.5 to VCC + 0.5V |
Clamp Diode Current (IIK, IOK) |
± 20 mA |
DC Output Current, per pin (IOUT) |
± 35 mA |
DC VCC or GND Current, per pin (ICC) |
± 70 mA |
Storage Temperature Range (TSTG) |
− 65° C to + 150° C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
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(Soldering 10 seconds) |
260° C |
Recommended Operating
Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
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DC Input or Output Voltage |
0 |
VCC |
V |
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(VIN, VOUT) |
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Operating Temperature Range (TA) |
− 40 |
+ 85 |
° C |
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Input Rise or Fall Times |
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(tr, tf) VCC = 2.0V |
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1000 |
ns |
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VCC = |
4.5V |
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500 |
ns |
VCC = |
6.0V |
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400 |
ns |
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/° C from 65° C to 85° C.
DC Electrical Characteristics (Note 4)
Symbol |
Parameter |
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Conditions |
VCC |
TA = |
25° C |
TA = − 40 to 85° C |
TA = |
− 55 to 125° C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
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2.0V |
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1.5 |
1.5 |
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1.5 |
V |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
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3.15 |
V |
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6.0V |
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4.2 |
4.2 |
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4.2 |
V |
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VIL |
Maximum LOW Level |
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2.0V |
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0.5 |
0.5 |
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0.5 |
V |
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Input Voltage |
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4.5V |
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1.35 |
1.35 |
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1.35 |
V |
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6.0V |
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1.8 |
1.8 |
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1.8 |
V |
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VOH |
Minimum HIGH Level |
VI N = |
VIH or VIL |
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Output Voltage |
|IOUT| ≤ |
20 µ A |
2.0V |
2.0 |
1.9 |
1.9 |
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1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
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4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
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5.9 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ |
6.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
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3.7 |
V |
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|IOUT| ≤ |
7.8 mA |
6.0V |
5.7 |
5.48 |
5.34 |
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5.2 |
V |
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VOL |
Maximum LOW Level |
VIN = |
VIH or VIL |
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Output Voltage |
|IOUT| ≤ |
20 µ A |
2.0V |
0 |
0.1 |
0.1 |
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0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
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0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
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0.1 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ |
6.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
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0.4 |
V |
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|IOUT| ≤ |
7.8 mA |
6.0V |
0.2 |
0.26 |
0.33 |
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0.4 |
V |
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IIN |
Maximum Input Current |
VIN = |
VCC or GND |
6.0V |
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± 0.1 |
± 1.0 |
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± 1.0 |
µ A |
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IOZ |
Maximum 3-STATE |
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VIN = |
VIH or VIL |
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Output Leakage |
VOUT = |
VCC or GND |
6.0V |
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± 0.5 |
± 5 |
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± 10 |
µ A |
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Current |
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G |
= VIH, G = VIL |
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ICC |
Maximum Quiescent |
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VIN = |
VCC or GND |
6.0V |
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8.0 |
80 |
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160 |
µ A |
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Supply Current |
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IOUT = |
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0 µ A |
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Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
MM74HC240
3 |
www.fairchildsemi.com |