Fairchild Semiconductor MM74HC245AWMX, MM74HC245ASJX, MM74HC245ACW, MM74HC245AMTC, MM74HC245AMTCX Datasheet
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September 1983
Revised February 1999
MM74HC245A
Octal 3-STATE Transceiver
General Description
The MM74HC245A 3-STATE bidirectional buffer utilizes advanced silicon-gate CMOS technology, and is intended for two-way asynchronous communication between data buses. It has high drive current outputs which enable high speed operation even when driving large bus capacitances. This circuit possesses the low power consumption and high noise immunity usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL circuits.
This device has an active LOW enable input G and a direction control input, DIR. When DIR is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from the B inputs to the A outputs. The MM74HC245A transfers true data from one bus to the other.
This device can drive up to 15 LS-TTL Loads, and does not have Schmitt trigger inputs. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
■Typical propagation delay: 13 ns
■Wide power supply range: 2–6V
■Low quiescent current: 80 μA maximum (74 HC)
■3-STATE outputs for connection to bus oriented systems
■High output drive: 6 mA (minimum)
■Same as the 645
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC245AWM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74HC245ASJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC245AMTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC245AN |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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Pin Assignments for DIP, SOIC, SOP and TSSOP |
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Control |
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Inputs |
Operation |
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DIR |
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G |
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L |
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L |
B data to A bus |
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L |
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H |
A data to B bus |
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H |
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X |
Isolation |
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H = HIGH Level |
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L = LOW Level |
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X = Irrelevant |
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Top View
Transceiver STATE-3 Octal MM74HC245A
© 1999 Fairchild Semiconductor Corporation |
DS005165.prf |
www.fairchildsemi.com |
MM74HC245A
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
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−1.5 to VCC +1.5V |
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DC Input Voltage DIR and |
G |
pins (VIN) |
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DC Input/Output Voltage (VIN, VOUT) |
−0.5 to VCC +0.5V |
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Clamp Diode Current (ICD) |
±20 mA |
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DC Output Current, per pin (IOUT) |
±35 mA |
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DC VCC or GND Current, per pin (ICC) |
±70 mA |
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Storage Temperature Range (TSTG) |
−65°C to +150°C |
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Power Dissipation (PD) |
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(Note 3) |
600 mW |
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S.O. Package only |
500 mW |
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Lead Temperature (TL) |
260°C |
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(Soldering 10 seconds) |
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DC Electrical Characteristics (Note 4)
Recommended Operating
Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
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(VIN, VOUT) |
0 |
VCC |
V |
Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise/Fall Times |
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(tr, tf) VCC = 2.0V |
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1000 |
ns |
VCC = 4.5V |
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500 |
ns |
VCC = 6.0V |
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400 |
ns |
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
Symbol |
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Parameter |
Conditions |
VCC |
TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level Input |
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2.0V |
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1.5 |
1.5 |
1.5 |
V |
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Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
V |
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VIL |
Maximum LOW Level Input |
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2.0V |
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0.5 |
0.5 |
0.5 |
V |
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Voltage |
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4.5V |
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1.35 |
1.35 |
1.35 |
V |
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6.0V |
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1.8 |
1.8 |
1.8 |
V |
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VOH |
Minimum HIGH Level Output |
VIN = VIH or VIL |
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Voltage |
|IOUT| ≤ 20 μA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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|IOUT| ≤ 7.8 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
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VOL |
Maximum LOW Level Output |
VIN = VIH or VIL |
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Voltage |
|IOUT| ≤ 20 μA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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|IOUT| ≤ 7.8 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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IIN |
Input Leakage |
VIN = VCC to GND |
6.0V |
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±0.1 |
±1.0 |
±1.0 |
μA |
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Current (G and DIR) |
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IOZ |
Maximum 3-STATE Output |
VOUT = VCC or GND |
6.0V |
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±0.5 |
±5.0 |
±10 |
μA |
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Leakage Current |
Enable |
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= VIH |
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G |
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ICC |
Maximum Quiescent Supply |
VIN = VCC or GND |
6.0V |
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8.0 |
80 |
160 |
μA |
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Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
MM74HC245A
3 |
www.fairchildsemi.com |
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