Fairchild Semiconductor MM74HCT574WMX, MM74HCT574SJ, MM74HCT574SJX, MM74HCT574MTCX, MM74HCT574CW Datasheet

February 1990

Revised May 1999

MM74HCT573 • MM74HCT574

Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop

General Description

The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic and pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground.

When the MM74HCT573 Latch Enable input is HIGH, the Q outputs will follow the D inputs. When the Latch Enable goes LOW, data at the D inputs will be retained at the outputs until Latch Enable returns HIGH again. When a high logic level is applied to the Output Control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

The MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive

going transitions of the Clock (CK) input. When a high logic level is applied to the Output Control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

The MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.

Features

■TTL input characteristic compatible

■Typical propagation delay: 18 ns

■Low input current: 1 μA maximum

■Low quiescent current: 80 μA maximum

■Compatible with bus-oriented systems

■Output drive capability: 15 LS-TTL loads

Ordering Codes:

Order Number	Package Number	Package Description
MM74HCT573WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MM74HCT573SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT573MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT573N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
MM74HCT574WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MM74HCT574SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT574MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT574N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Flop-Flip Type-D Octal STATE-3 • Latch Type-D Octal MM74HCT574 • MM74HCT573

© 1999 Fairchild Semiconductor Corporation

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MM74HCT573 • MM74HCT574

Connection Diagrams

Top View

MM74HCT573

Top View

MM74HCT574

Truth Tables

MM74HCT573

	Output	LE	Data	Output
	Control
	L	H	H	H
	L	H	L	L
	L	L	X	Q0
	H	X	X	Z

H = HIGH Level

L = LOW Level

Q0 = Level of output before steady-state input conditions were established. Z = High Impedance State

MM74HCT574

	Output	LE	Data	Output
	Control
	L	−	H	H
	L	−	L	L
	L	L	X	Q0
	H	X	X	Z

H = HIGH Level

L = LOW Level

Q0 = Level of output before steady-state input conditions were established. X = Don’t Care

Z = High Impedance State

− = Transition from LOW-to-HIGH

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2

Absolute Maximum Ratings(Note 1)

(Note 2)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC+ 1.5V
DC Output Voltage (VOUT)	−0.5 to VCC+ 0.5V
Clamp Diode Current (IIK, IOK)	± 20 mA
DC Output Current, per pin (IOUT)	± 35 mA
DC VCC or GND Current, per pin (ICC)	± 70 mA
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 3)	600 mW
S. O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	4.5	5.5	V
DC Input or Output Voltage
(VIN, VOUT)	0	VCC	V
Operating Temperature Range (TA)	−40	+85	°C
Input Rise or Fall Times
tr, tf		500	ns

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics

VCC = 5V ± 10% (unless otherwise specified)
Symbol	Parameter	Conditions	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
			Typ		Guaranteed Limits
VIH	Minimum HIGH Level			2.0	2.0	2.0	V
	Input Voltage
VIL	Maximum LOW Level			0.8	0.8	0.8	V
	Input Voltage
VOH	Minimum HIGH Level	VIN = VIH or VIL
	Output Voltage	|IOUT| = 20 μA	VCC	VCC − 0.1	VCC − 0.1	VCC − 0.1	V
		|IOUT| = 6.0 mA, VCC = 4.5V	4.2	3.98	3.84	3.7
		|IOUT| = 7.2 mA, VCC = 5.5V	5.7	4.98	4.84	4.7
VOL	Maximum LOW Level	VIN = VIH or VIL
	Voltage	|IOUT| = 20 μA	0	0.1	0.1	0.1	V
		|IOUT| = 6.0 mA, VCC = 4.5V	0.2	0.26	0.33	0.4
		|IOUT| = 7.2 mA, VCC = 5.5V	0.2	0.26	0.33	0.4
IIN	Maximum Input	VIN = VCC or GND,		±0.1	±1.0	±1.0	μA
	Current	VIH or VIL
IOZ	Maximum 3-STATE	VOUT = VCC or GND
	Output Leakage	Enable = VIH or VIL		±0.5	±5.0	±10	μA
	Current
ICC	Maximum Quiescent	VIN = VCC or GND		8.0	80	160	μA
	Supply Current	IOUT = 0 μA
		VIN = 2.4V or 0.5V (Note 4)		1.5	1.8	2.0	mA

Note 4: Measured per pin. All others tied to VCC or ground.

MM74HCT574 • MM74HCT573

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