Fairchild Semiconductor MM74HC74ASJX, MM74HC74ACW, MM74HC74AM, MM74HC74AMTC, MM74HC74AMTCX Datasheet

September 1983

Revised February 1999

MM74HC74A

Dual D-Type Flip-Flop with Preset and Clear

General Description

The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads.

This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positivegoing transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.

The 74HC logic family is functionally and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

■Typical propagation delay: 20 ns

■Wide power supply range: 2–6V

■Low quiescent current: 40 μA maximum (74HC Series)

■Low input current: 1 μA maximum

■Fanout of 10 LS-TTL loads

Ordering Code:

Order Number	Package Number	Package Description
MM74HC74AM	M14A	14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC74ASJ	M14D	14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC74AMTC	MTC14	14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC74AN	N14A	14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP		Inputs			Outputs
	PR	CLR	CLK	D	Q			Q
	L	H	X	X	H			L
	H	L	X	X	L			H
	L	L	X	X	H (Note 1)	H (Note 1)
	H	H	−	H	H			L
	H	H	−	L	L			H
	H	H	L	X	Q0
							Q		0
	Note: Q0 = the level of Q before the indicated input conditions were estab-
	lished.
	Note 1: This configuration is nonstable; that is, it will not persist when pre-
	set and clear inputs return to their inactive (HIGH) level.

Clear and Preset with Flop-Flip Type-D Dual MM74HC74A

© 1999 Fairchild Semiconductor Corporation

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MM74HC74A

Logic Diagram

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2

Absolute Maximum Ratings(Note 2)

(Note 3)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC +1.5V
DC Output Voltage (VOUT)	−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)	±20 mA
DC Output Current, per pin (IOUT)	±25 mA
DC VCC or GND Current, per pin	±50 mA
(ICC)
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 4)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

DC Electrical Characteristics (Note 5)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	2	6	V
DC Input or Output Voltage	0	VCC	V
(VIN, OUT)	−40	+85	°C
Operating Temperature Range (TA)
Input Rise or Fall Times
(tr, tf) VCC = 2.0V		1000	ns
VCC = 4.5V		500	ns
VCC = 6.0V		400	ns

Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 3: Unless otherwise specified all voltages are referenced to ground.

Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

Symbol	Parameter	Conditions	VCC	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
				Typ		Guaranteed Limits
VIH	Minimum HIGH Level		2.0V		1.5	1.5	1.5	V
	Input Voltage		4.5V		3.15	3.15	3.15	V
			6.0V		4.2	4.2	4.2	V
VIL	Maximum LOW Level		2.0V		0.5	0.5	0.5	V
	Input Voltage		4.5V		1.35	1.35	1.35	V
			6.0V		1.8	1.8	1.8	V
VOH	Minimum HIGH Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	2.0	1.9	1.9	1.9	V
			4.5V	4.5	4.4	4.4	4.4	V
			6.0V	6.0	5.9	5.9	5.9	V
		VIN = VIH or VIL
		|IOUT| ≤ 4.0 mA	4.5V	4.3	3.98	3.84	3.7	V
		|IOUT| ≤ 5.2 mA	6.0V	5.2	5.48	5.34	5.2	V
VOL	Maximum LOW Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	0	0.1	0.1	0.1	V
			4.5V	0	0.1	0.1	0.1	V
			6.0V	0	0.1	0.1	0.1	V
		VIN = VIH or VIL
		|IOUT| ≤ 4.0 mA	4.5V	0.2	0.26	0.33	0.4	V
		|IOUT| ≤ 5.2 mA	6.0V	0.2	0.26	0.33	0.4	V
IIN	Maximum Input	VIN = VCC or GND	6.0V		±0.1	±1.0	±1.0	μA
	Current
ICC	Maximum Quiescent	VI N =VCC or GND	6.0V		4.0	40	80	μA
	Supply Current	IOUT = 0 μA

Note 5: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

MM74HC74A

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