Fairchild Semiconductor MM74HC374WMX, MM74HC374SJX, MM74HC374N, MM74HC374MTC, MM74HC374WM Datasheet

September 1983

Revised February 1999

MM74HC374

3-STATE Octal D-Type Flip-Flop

General Description

The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system.

These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what

signals are present at the other inputs and the state of the storage elements.

The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

■Typical propagation delay: 20 ns

■Wide operating voltage range: 2–6V

■Low input current: 1 μA maximum

■Low quiescent current: 80 μA maximum

■Compatible with bus-oriented systems

■Output drive capability: 15 LS-TTL loads

Ordering Code:

Order Number	Package Number	Package Description
MM74HC374WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC374SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC374MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC374N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP		Output	Clock	Data	Output
		Control
		L	−	H	H
		L	−	L	L
		L	L	X	Q0
		H	X	X	Z

H = HIGH Level

L = LOW Level

X = Don't Care

− = Transition from LOW-to-HIGH Z = High Impedance State

Q0 = The level of the output before steady state input conditions were

established

Top View

Flop-Flip Type-D Octal STATE-3 MM74HC374

© 1999 Fairchild Semiconductor Corporation

DS005336.prf

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MM74HC374

Absolute Maximum Ratings(Note 1)

(Note 2)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC +1.5V
DC Output Voltage (VOUT)	−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)	±20 mA
DC Output Current, per pin (IOUT)	±35 mA
DC VCC or GND Current, per pin (ICC)	±70 mA
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	2	6	V
DC Input or Output Voltage
(VIN, VOUT)	0	VCC	V
Operating Temperature Range (TA)	−40	+85	°C
Input Rise or Fall Times
(tr, tf) VCC = 2.0V		1000	ns
VCC = 4.5V		500	ns
VCC = 6.0V		400	ns

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics

Symbol	Parameter	Conditions	VCC	TA = 25°C		TA = −40 to 85°C	TA = −55 to 125°C	Units
				Typ		Guaranteed Limits
VIH	Minimum HIGH Level		2.0V		1.5	1.5	1.5	V
	Input Voltage		4.5V		3.15	3.15	3.15	V
			6.0V		4.2	4.2	4.2	V
VIL	Maximum LOW Level		2.0V		0.5	0.5	0.5	V
	Input Voltage		4.5V		1.35	1.35	1.35	V
			6.0V		1.8	1.8	1.8	V
VOH	Minimum HIGH Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	2.0	1.9	1.9	1.9	V
			4.5V	4.5	4.4	4.4	4.4	V
			6.0V	6.0	5.9	5.9	5.9	V
		VIN = VIH or VIL
		|IOUT| ≤ 6.0 mA	4.5V	4.2	3.98	3.84	3.7	V
		|IOUT| ≤ 7.8 mA	6.0V	5.7	5.48	5.34	5.2	V
VOL	Maximum LOW Level	VIN = VIH or VIL
	Output Voltage	|IOUT| ≤ 20 μA	2.0V	0	0.1	0.1	0.1	V
			4.5V	0	0.1	0.1	0.1	V
			6.0V	0	0.1	0.1	0.1	V
		VIN = VIH or VIL
		|IOUT| ≤ 6.0 mA	4.5V	0.2	0.26	0.33	0.4	V
		|IOUT| ≤ 7.8 mA	6.0V	0.2	0.26	0.33	0.4	V
IIN	Maximum Input	VIN = VCC or GND	6.0V		±0.1	±1.0	±1.0	μA
	Current
IOZ	Maximum 3-STATE	VIN = VIH, OC = VIH	6.0V		±0.5	±5	±10	μA
	Output Leakage	VOUT = VCC or GND
	Current
ICC	Maximum Quiescent	VIN = VCC or GND	6.0V		8.0	80	160	μA
	Supply Current	IOUT = 0 μA

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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AC Electrical Characteristics

VCC = 5V, TA = 25°C, tr = tf = 6 ns

	Symbol	Parameter	Conditions	Typ	Guaranteed	Units
					Limit
	fMAX	Maximum Operating		50	35	MHz
		Frequency
	tPHL, tPLH	Maximum Propagation	CL=45 pF	20	32	ns
		Delay Clock to Q
	tPZH, tPZL	Maximum Output Enable	RL= kΩ
		Time	CL=45 pF	19	28	ns
	tPHZ, tPLZ	Maximum Output Disable	RL= kΩ	17	25	ns
		Time	CL=5 pF
	tS	Minimum Setup Time			20	ns
	tH	Minimum Hold Time			5	ns
	tW	Minimum Pulse Width		9	16	ns

MM74HC374

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