Fairchild Semiconductor MM74HCT164N, MM74HCT164SJ, MM74HCT164CW, MM74HCT164SJX, MM74HCT164M Datasheet
February 1984
Revised February 1999
MM74HCT164
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM74HCT164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices.
This 8-bit shift register has gated serial inputs and CLEAR. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A HIGH level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input.
The 74HCT logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
Features
■Typical propagation delay: 20 ns
■Low quiescent current: 40 μA maximum (74HCT Series)
■Low input current: 1 μA maximum
■Fanout of 10 LS-TTL loads
■TTL input compatible
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HCT164M |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
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MM74HCT164SJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HCT164N |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP) JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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Pin Assignments for DIP, SOIC and SOP |
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Inputs |
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Outputs |
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Clear |
Clock |
A |
B |
QA |
QB ... |
QH |
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L |
X |
X |
X |
L |
L |
L |
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H |
L |
X |
X |
QAO |
QBO |
QHO |
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H |
− |
H |
H |
H |
QAn |
QGn |
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H |
− |
L |
X |
L |
QAn |
QGn |
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H |
− |
X |
L |
L |
QAn |
QGn |
H = HIGH Level (steady state) L = LOW Level (steady state)
X = Irrelevant (any input, including transitions) − = Transition from LOW-to-HIGH level.
QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indicated steady state input conditions were established.
QAn, QGn = The level of QA or QG before the most recent − transition of the clock; indicated a one-bit shift.
Top View
Register Shift out-in/Parallel-Serial Bit-8 MM74HCT164
© 1999 Fairchild Semiconductor Corporation |
DS005765.prf |
www.fairchildsemi.com |
MM74HCT164
Logic Diagram
www.fairchildsemi.com |
2 |
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