January 1992
Revised May 1999
MM74HC594
8-Bit Shift Register with Output Registers
General Description
This high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clears are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.
The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
■Low quiescent current: 80 μA maximum
■Low input current: 1 μA maximum
■8-bit serial-in, parallel-out shift register with storage
■Wide operating voltage range: 2V to 6V
■Cascadable
■Shift register has direct clear
■Guaranteed shift frequency: DC to30 MHz
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC594M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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MM74HC594N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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RCK |
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SCK |
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SCLR |
RCLR |
Function |
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X |
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X |
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X |
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L |
Storage Register cleared |
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X |
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X |
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L |
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X |
Shift Register cleared |
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Q’H = 0 |
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X |
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− |
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H |
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H |
Shift Register clocked |
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QN = Qn−1, Q0 = SER |
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Contents of Shift |
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− |
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X |
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H |
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H |
Register transferred |
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to output latches |
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Registers Output with Register Shift Bit-8 MM74HC594
© 1999 Fairchild Semiconductor Corporation |
DS010915.prf |
www.fairchildsemi.com |
MM74HC594
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1) |
Recommended Operation |
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(Note 2) |
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Conditions |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
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DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
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Min |
Max |
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DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Supply Voltage (VCC) |
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2 |
6 |
V |
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Clamp Diode Current (IIK, IOK) |
±20 mA |
DC Input or Output Voltage |
0 |
VCC |
V |
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DC Output Current, per pin (IOUT) |
±35 mA |
(VIN, VOUT) |
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DC VCC or GND Current, per pin (ICC) |
±70 mA |
Operating Temperature Range (TA) −40 |
+85 |
°C |
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Storage Temperature Range (TSTG) |
−65°C to +150°C |
Input Rise or Fall Times |
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Power Dissipation (PD) |
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(tr, tf) |
VCC = 2.0V |
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1000 |
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(Note 3) |
600 mW |
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VCC = 4.5V |
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500 |
ns |
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S.O. Package only |
500 mW |
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VCC = 6.0V |
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400 |
ns |
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Lead Temperature (TL) |
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Note 1: Absolute Maximum Ratings are those values beyond which dam- |
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(Soldering 10 seconds) |
260°C |
age to the device may occur. |
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Note 2: Unless otherwise specified all voltages are referenced to ground. |
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Note 3: Power Dissipation temperature derating—plastic “N” package: −12 |
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mW/°C from 65°C to 85°C. |
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DC Electrical Characteristics (Note 4) |
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Symbol |
Parameter |
Conditions |
VCC |
TA = 25°C |
TA = −40 to 85°C |
Units |
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Typ |
Guaranteed Limits |
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VIH |
Minimum HIGH Level |
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2.0V |
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1.5 |
1.5 |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
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V |
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6.0V |
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4.2 |
4.2 |
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VIL |
Maximum LOW Level |
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2.0V |
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0.5 |
0.5 |
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Input Voltage |
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4.5V |
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1.35 |
1.35 |
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V |
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6.0V |
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1.8 |
1.8 |
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VOH |
Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
2.0 |
1.9 |
1.9 |
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V |
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4.5V |
4.5 |
4.4 |
4.4 |
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6.0V |
6.0 |
5.9 |
5.9 |
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Q’H |
VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
4.5V |
4.7 |
3.98 |
3.84 |
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V |
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|IOUT| ≤ 5.2 mA |
6.0V |
5.2 |
5.48 |
5.34 |
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QA thru QH |
VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
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V |
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|IOUT| ≤ 7.8 mA |
6.0V |
5.7 |
5.48 |
5.34 |
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VOL |
Maximum LOW Level |
VIN = VIH or VIL |
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Output Voltage |
|IOUT| ≤ 20 μA |
2.0V |
0 |
0.1 |
0.1 |
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V |
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4.5V |
0 |
0.1 |
0.1 |
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6.0V |
0 |
0.1 |
0.1 |
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Q’H |
VIN = VIH or VIL |
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|IOUT| ≤ 4.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
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V |
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|IOUT| ≤ 5.2 mA |
6.0V |
0.2 |
0.26 |
0.33 |
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QA thru QH |
VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
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V |
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|IOUT| ≤ 7.8 mA |
6.0V |
0.2 |
0.26 |
0.33 |
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IIN |
Maximum Input |
VIN = VCC or GND |
6.0V |
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±0.1 |
±1.0 |
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μA |
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Current |
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ICC |
Maximum Quiescent |
VIN = VCC or GND |
6.0V |
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8.0 |
80 |
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μA |
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Supply Current |
IOUT = 0 μA |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
MM74HC594
3 |
www.fairchildsemi.com |
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