September 1983
Revised February 1999
MM74HC589
8-Bit Shift Registers with Input Latches and 3-STATE Serial Output
General Description
The MM74HC589 high speed shift register utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.
The MM74HC589 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8- bit shift register. Data can also be entered serially the shift register through the SER pin. Both the storage register and shift register have positive-edge triggered clocks, RCK and SCK, respectively. SLOAD pin controls parallel LOAD or serial shift operations for the shift register. The shift register has a 3-STATE output to enable the wire-ORing of multiple devices on a serial bus.
The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
■8-bit parallel storage register inputs
■Wide operating voltage range: 2V–6V
■Shift register has direct overriding load
■Guaranteed shift frequency. . . DC to 30 MHz
■Low quiescent current: 80 μA maximum (74HC Series)
■3-STATE output for ‘Wire-OR'
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74HC589M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
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MM74HC589SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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MM74HC589MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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MM74HC589N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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Pin Assignments for DIP, SOIC, SOP and TSSOP |
RCK |
SCK |
SLOAD |
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OE |
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Function |
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X |
X |
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X |
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H |
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QH in Hi-Z State |
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X |
X |
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X |
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L |
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QH is enabled |
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− |
X |
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X |
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X |
Data loaded into input latches |
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− |
X |
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L |
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X |
Data loaded into shift register |
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from pins |
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H or L |
X |
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L |
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X |
Data loaded from latches to |
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shift register |
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X |
− |
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H |
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X |
Shift register is shifted. Data |
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Top View |
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on SER pin is shifted in. |
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− |
− |
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H |
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X |
Data is shifted in shift register, |
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and data is loaded into latches |
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Output Serial STATE-3 and Latches Input with Registers Shift Bit-8 MM74HC589
© 1999 Fairchild Semiconductor Corporation |
DS005368.prf |
www.fairchildsemi.com |
MM74HC589
Block Diagram (positive logic)
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
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Supply Voltage (VCC) |
−0.5 to +7.0V |
DC Input Voltage (VIN) |
−1.5 to VCC +1.5V |
DC Output Voltage (VOUT) |
−0.5 to VCC +0.5V |
Clamp Diode Current (IIK, IOK) |
±20 mA |
DC Output Current, per pin (IOUT) |
±25 mA |
DC VCC or GND Current, per pin (ICC) |
±50 mA |
Storage Temperature Range (TSTG) |
−65°C to +150°C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temperature (TL) |
260°C |
(Soldering 10 seconds) |
Recommended Operating
Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
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(VIN, VOUT) |
0 |
VCC |
V |
Operating Temperature Range (TA) |
−40 |
+85 |
°C |
Input Rise or Fall Times |
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(tr, tf) VCC = 2.0V |
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1000 |
ns |
VCC = 4.5V |
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500 |
ns |
VCC = 6.0V |
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400 |
ns |
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics |
(Note 4) |
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Symbol |
Parameter |
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Conditions |
VCC |
TA = 25°C |
TA = −40 to 85°C |
TA = −55 to 125°C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
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2.0V |
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1.5 |
1.5 |
1.5 |
V |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
V |
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VIL |
Maximum LOW Level |
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2.0V |
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0.5 |
0.5 |
0.5 |
V |
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Input Voltage |
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4.5V |
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1.35 |
1.35 |
1.35 |
V |
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6.0V |
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1.8 |
1.8 |
1.8 |
V |
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VOH |
Minimum HIGH Level |
VIN = VIH or VIL |
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Output Voltage |
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|IOUT| ≤ 20 μA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
4.5V |
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3.98 |
3.84 |
3.7 |
V |
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|IOUT| ≤ 7.8 mA |
6.0V |
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5.48 |
5.34 |
5.2 |
V |
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VOL |
Maximum LOW Level |
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VIN = VIH or VIL |
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Output Voltage |
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|IOUT| ≤ 20 μA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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VIN = VIH or VIL |
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|IOUT| ≤ 6.0 mA |
4.5V |
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0.26 |
0.33 |
0.4 |
V |
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|IOUT| ≤ 7.8 mA |
6.0V |
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0.26 |
0.33 |
0.4 |
V |
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IIN |
Maximum Input |
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VIN = VCC or GND |
6.0V |
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±0.1 |
±1.0 |
±1.0 |
μA |
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Current |
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ICC |
Maximum Quiescent |
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VIN = VCC or GND |
6.0V |
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8.0 |
80 |
160 |
μA |
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Supply Current |
IOUT = 0 μA |
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IOZ |
Maximum 3-STATE |
Output in High |
6.0V |
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±0.5 |
±5.0 |
±10.0 |
μA |
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Leakage Current |
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Impedance State |
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VIN = VIL or VIH |
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VOUT = VCC or GND |
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= VIH |
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OE |
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Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
MM74HC589
3 |
www.fairchildsemi.com |
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