Fairchild Semiconductor MM74HCT74SJX, MM74HCT74N, MM74HCT74MX, MM74HCT74MTCX, MM74HCT74SJ Datasheet

February 1984

Revised January 1999

MM74HCT74

Dual D-Type Flip-Flop with Preset and Clear

General Description

The MM74HCT74 utilizes advanced silicon-gate CMOS technology to achieve operation speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads.

This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positivegoing transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.

The 74HCT logic family is functionally and pin-out compatible with the standard 74LS logic family. All inputs are pro-

tected from damage due to static discharge by internal diode clamps to VCC and ground.

MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.

Features

■Typical propagation delay: 20 ns

■Low quiescent current: 40 μA maximum (74HCT Series)

■Low input current: 1 μA maximum

■Fanout of 10 LS-TTL loads

■Meta-stable hardened

Ordering Code:

Order Number	Package Number	Package Description
MM74HCT74M	M14A	14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HCT74SJ	M14D	14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M74HCT74MTC	MTC14	14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT74N	N14A	14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP			Inputs			Outputs
		PR	CLR	CLK	D	Q
									Q
		L	H	X	X	H			L
		H	L	X	X	L			H
		L	L	X	X	H			H
						(Note 1)	(Note 1)
		H	H	−	H	H			L
		H	H	−	L	L			H
		H	H	L	X	Q0
								Q0
	Q0 = the level of Q before the indicated input conditions were established.
	Note 1: This configuration is nonstable; that is, it will not persist when pre-
	set and clear inputs return to their inactive (HIGH) level.

Clear and Preset with Flop-Flip Type-D Dual MM74HCT74

© 1999 Fairchild Semiconductor Corporation

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MM74HCT74

Logic Diagram

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2

Absolute Maximum Ratings(Note 2)

(Note 3)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC +1.5V
DC Output Voltage (VOUT)	−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)	±20 mA
DC Output Current, per pin (IOUT)	±25 mA
DC VCC or GND Current, per pin (ICC)	±50 mA
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 4)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	4.5	5.5	V
DC Input or Output Voltage
(VIN, VOUT)	0	VCC	V
Operating Temperature Range (TA)	−40	+85	°C
Input Rise or Fall Times
(tr, tf)		500	ns

Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 3: Unless otherwise specified all voltages are referenced to ground.

Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics

VCC = 5V ±10% (unless otherwise specified)
Symbol	Parameter	Conditions	TA = 25°C		TA = −40° to 85°C	TA = −55 to 125°C	Units
			Typ		Guaranteed Limits
VIH	Minimum HIGH Level			2.0	2.0	2.0	V
	Input Voltage
VIL	Maximum LOW Level			0.8	0.8	0.8	V
	Input Voltage
VOH	Minimum HIGH Level	VIN = VIH or VIL
	Output Voltage	|IOUT| = 20 μA	VCC	VCC− 0.1	VCC− 0.1	VCC− 0.1	V
		|IOUT| = 4.0 mA, VCC = 4.5V	4.2	3.98	3.84	3.7	V
		|IOUT| = 4.8 mA, VCC = 5.5V	5.2	4.98	4.84	4.7	V
VOL	Maximum LOW Level	VIN = VIH or VIL
	Voltage	|IOUT| = 20 μA	0	0.1	0.1	0.1	V
		|IOUT| = 4.0 mA, VCC = 4.5V	0.2	0.26	0.33	0.4	V
		|IOUT| = 4.8 mA, VCC = 5.5V	0.2	0.26	0.33	0.4	V
IIN	Maximum Input	VIN = VCC or GND,		±0.0.5	±0.5	±1.0	μA
	Current	VIH or VIL
ICC	Maximum Quiescent	VIN = VCC or GND
	Supply Current	IOUT = 0 μA		2.0	20	80	μA
		VIN = 2.4V or 0.5V (Note 5)		0.3	0.4	0.5	mA

Note 5: This is measured per pin. All other inputs are held at VCC Ground.

MM74HCT74

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