Fairchild Semiconductor MM74HC540WMX, MM74HC540SJX, MM74HC540N, MM74HC540MTC, MM74HC540WM Datasheet

September 1983

Revised February 1999

MM74HC540 • MM74HC541

Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer

General Description

The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate CMOS technology. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity, and low power consumption. Both devices have a fanout of 15 LS-TTL equivalent inputs.

The MM74HC540 is an inverting buffer and the MM74HC541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high-imped- ance state.

In order to enhance PC board layout, the MM74HC540 and MM74HC541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features

■Typical propagation delay: 12 ns

■3-STATE outputs for connection to system buses

■Wide power supply range: 2–6V

■Low quiescent current: 80 μA maximum (74HC Series)

■Output current: 6 mA

Ordering Code:

Order Number	Package Number	Package Description
MM74HC540WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC540SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC541WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC541SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC541N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View	Top View
MM74HC540	MM74HC541

Buffer STATE-3 Octal • Buffer STATE-3 Octal Inverting MM74HC541 • MM74HC540

© 1999 Fairchild Semiconductor Corporation

DS005341.prf

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MM74HC540 • MM74HC541

Absolute Maximum Ratings(Note 1)

(Note 2)
Supply Voltage (VCC)	−0.5 to +7.0V
DC Input Voltage (VIN)	−1.5 to VCC +1.5V
DC Output Voltage (VOUT)	−0.5 to VCC +0.5V
Clamp Diode Current (ICD)	±20 mA
DC Output Current, per pin (IOUT)	±35 mA
DC VCC or GND Current,	±70 mA
per pin (ICC)
Storage Temperature Range (TSTG)	−65°C to +150°C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temperature (TL)	260°C
(Soldering 10 seconds)

DC Electrical Characteristics (Note 4)

Recommended Operating

Conditions

	Min	Max	Units
Supply Voltage (VCC)	2	6	V
DC Input or Output Voltage
(VIN, VOUT)	0	VCC	V
Operating Temperature Range (TA)	−40	+85	°C
Input Rise or Fall Times
(tr, tf) VCC = 2.0V		1000	ns
VCC = 4.5V		500	ns
VCC = 6.0V		400	ns

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.

Symbol

Parameter

Conditions

VCC

TA = 25°C

TA = −40 to 85°C

TA = −55 to 125°C

Units

Typ

Guaranteed Limits

VIH

Minimum HIGH Level

2.0V

1.5

1.5

1.5

V

Input Voltage

4.5V

3.15

3.15

3.15

V

6.0V

4.2

4.2

4.2

V

VIL

Maximum LOW Level

2.0V

0.5

0.5

0.5

V

Input Voltage

4.5V

1.35

1.35

1.35

V

6.0V

1.8

1.8

1.8

V

VOH

Minimum HIGH Level

VIN = VIH or VIL

Output Voltage

|IOUT| ≤ 20 μA

2.0V

2.0

1.9

1.9

1.9

V

4.5V

4.5

4.4

4.4

4.4

V

6.0V

6.0

5.9

5.9

5.9

V

VIN = VIH or VIL

|IOUT| ≤ 6.0 mA

4.5V

4.2

3.98

3.84

3.7

V

|IOUT| ≤ 7.8 mA

6.0V

5.7

5.48

5.34

5.2

V

VOL

Maximum LOW Level

VIN = VIH or VIL

Output Voltage

|IOUT| ≤ 20 μA

2.0V

0

0.1

0.1

0.1

V

4.5V

0

0.1

0.1

0.1

V

6.0V

0

0.1

0.1

0.1

V

VIN = VIH or VIL

|IOUT| ≤ 6.0 mA

4.5V

0.2

0.26

0.33

0.4

V

|IOUT| ≤ 7.8 mA

6.0V

0.2

0.26

0.33

0.4

V

IIN

Maximum Input

VIN = VCC or GND

6.0V

±0.1

±1.0

±1.0

μA

Current

IOZ

Maximum 3-STATE

V

= V or V

,

= V

6.0V

±0.5

±5

±10

μA

G

IH

IN

IH

IL

Output Leakage

VOUT = VCC or GND

Current

ICC

Maximum Quiescent

VIN = VCC or GND

6.0V

8.0

80

160

μA

Supply Current

IOUT = 0 μA

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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