October 1987
Revised January 1999
MM74C175
Quad D-Type Flip-Flop
General Description
The MM74C175 consists of four positive-edge triggered D- type flip-flops implemented with monolithic CMOS technology. Both are true and complemented outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and a common clear. Information at the D-type inputs meeting the set-up time requirements is transferred to the Q outputs on the posi- tive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all four Q outputs to logical “0” and Q's to logical “1”.
All inputs are protected from static discharge by diode clamps to VCC and GND.
Features
■Wide supply voltage range: 3V to 15V
■Guaranteed noise margin: 1.0V
■High noise immunity: 0.45 VCC (typ.)
■Low power TTL compatibility: Fan out of 2 driving 74L
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74C175M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow |
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MM74C175N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
Each Flip-Flop
Pin Assignments for DIP and SOIC
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Inputs |
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Outputs |
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Clear |
Clock |
D |
Q |
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Q |
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L |
X |
X |
L |
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H |
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H |
− |
H |
H |
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L |
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H |
− |
L |
L |
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H |
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H |
H |
X |
NC |
NC |
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H |
L |
X |
NC |
NC |
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H = HIGH Level
L = LOW Level
X = Irrelevant
− = Transition from LOW-to-HIGH level NC = No Change
Top View
Flop-Flip Type-D Quad MM74C175
© 1999 Fairchild Semiconductor Corporation |
DS005900.prf |
www.fairchildsemi.com |
MM74C175
Block Diagrams
Typical One of Four
www.fairchildsemi.com |
2 |
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