October 1987
Revised January 1999
MM74C74 Dual D-Type Flip-Flop
© 1999 Fairchild Semiconductor Corporation DS005885.prf www.fairchildsemi.com
MM74C74
Dual D-Type Flip-Flop
General Description
The MM74C74 dual D- type fli p-f lop i s a m on ol ithic comple-
mentary MOS (CMOS ) integrated circuit constructed w ith
N- and P-channel enhancement transisto rs. Each flip-flop
has independent data, preset, clear and clock inputs and Q
and Q
outputs. The logic level pres ent at the data input is
transferred to the output during the positive going transition
of the clock pulse. Preset or clear is independent of the
clock an d acc om pl i s hed by a low l evel at t he pr e set or c lea r
input.
Features
■ Supply voltage range: 3V to 15V
■ Tenth power TTL compatible: Drive 2 LPT
2
L loads
■ High noise immunity: 0.45 V
CC
(typ.)
■ Low power: 50 nW (typ.)
■ Medium speed operation: 10 MHz (typ.) with 10V
supply
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm system
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Note: A logic “0” on clear s et s Q t o logic “0”.
A logic “0” on preset se ts Q to logic “1”.
Top View
Truth Table
Note 1: No change in output from previous state.
Order Number Package Number Package Description
MM74C74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Preset Clear Q
n
Q
n
0000
0110
1001
11Q
n
(Note 1) Q
n
(Note 1)