October 1987
Revised January 1999
MM74C373 • MM74C374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74C373 and MM74C374 are integrated, complementary MOS (CMOS), 8-bit storage elements with 3- STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
The MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again.
The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on posi- tive-going transitions of the CLOCK input.
Both the MM74C373 and the MM74C374 are being assembled in 20-pin dual-in-line packages with 0.300” pin centers.
Features
■Wide supply voltage range: 3V to 15V
■High noise immunity: 0.45 VCC (typ.)
■Low power consumption
■TTL compatibility:
Fan out of 1driving standard TTL
■Bus driving capability
■3-STATE outputs
■Eight storage elements in one package
■Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control inputs
■20-pin dual-in-line package with 0.300” centers takes half the board space of a 24-pin package
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74C373M |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74C373N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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MM74C374M |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide |
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MM74C374N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Flop-Flip Type-D Octal STATE-3 • Latch Type-D Octal STATE-3 MM74C374 • MM74C373
© 1999 Fairchild Semiconductor Corporation |
DS005906.prf |
www.fairchildsemi.com |
MM74C373 • MM74C374
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C373 |
MM74C374 |
Top View |
Top View |
Truth Tables
MM74C373
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Output |
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LATCH |
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D |
Q |
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Disable |
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ENABLE |
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L |
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H |
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H |
H |
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L |
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H |
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L |
L |
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L |
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L |
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X |
Q |
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H |
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X |
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X |
Hi-Z |
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L = LOW logic level H = HIGH logic level X = Irrelevant
= LOW-to-HIGH logic level transition Q = Preexisting output level
Hi-Z = High impedance output state
MM74C374
Output |
Clock |
D |
Q |
Disable |
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L |
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H |
H |
L |
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L |
L |
L |
L |
X |
Q |
L |
H |
X |
Q |
H |
X |
X |
Hi-Z |
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2 |
Block Diagrams
MM74C373 (1 of 8 Latches)
MM74C374 (1 of 8 Flip-Flops)
MM74C374 • MM74C373
3 |
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MM74C373 • MM74C374
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin |
−0.3V to VCC + 0.3V |
Operating Temperature Range (TA) |
−40°C to +85°C |
MM74C373 |
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Storage Temperature Range (TS) |
−65°C to +150°C |
Power Dissipation |
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Dual-In-Line |
700 mW |
Small Outline |
500 mW |
Operating VCC Range |
3V to 15V |
Absolute Maximum VCC |
18V |
Lead Temperature (TL) |
260°C |
(Soldering, 10 seconds) |
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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CMOS TO CMOS |
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VIN(1) |
Logical “1” Input Voltage |
VCC = 5V |
3.5 |
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V |
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VCC = 10V |
8.0 |
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V |
VIN(0) |
Logical “0” Input Voltage |
VCC = 5V |
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1.5 |
V |
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VCC = 10V |
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2.0 |
V |
VOUT(1) |
Logical “1” Output Voltage |
VCC = 5V, IO = −10 μA |
4.5 |
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V |
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VCC = 10V, IO = −10 μA |
9.0 |
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V |
VOUT(0) |
Logical “0” Output Voltage |
VCC = 5V, IO = 10 μA |
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0.5 |
V |
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VCC = 10V, IO = 10 μA |
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1.0 |
V |
IIN(1) |
Logical “1” Input Current |
VCC = 15V, VIN = 15V |
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0.005 |
1.0 |
μA |
IIN(0) |
Logical “0” Input Current |
VCC = 15V, VIN = 0V |
−1.0 |
−0.005 |
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μA |
IOZ |
3-STATE Leakage Current |
VCC = 15V, VO = 15V |
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0.005 |
1.0 |
μA |
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VCC = 15V, VO = 0V |
−1.0 |
−0.005 |
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μA |
ICC |
Supply Current |
VCC = 15V |
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0.05 |
300 |
μA |
CMOS/LPTTL |
INTERFACE |
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VIN(1) |
Logical “1” Input Voltage |
VCC = 4.75V |
VCC − 1.5 |
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V |
VIN(0) |
Logical “0” Input Voltage |
VCC = 4.75V |
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0.8 |
V |
VOUT(1) |
Logical “1” Output Voltage |
VCC = 4.75V, IO = −360 μA |
VCC − 0.4 |
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V |
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VCC = 4.75V, IO = −1.6 mA |
2.4 |
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V |
VOUT(0) |
Logical “0” Output Voltage |
VCC = 4.75V, IO = 1.6 mA |
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0.4 |
V |
OUTPUT DRIVE (Short Circuit Current) |
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ISOURCE |
Output Source Current |
VCC = 5V, VOUT = 0V |
−12 |
−24 |
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mA |
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TA = 25°C (Note 2) |
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ISOURCE |
Output Source Current |
VCC = 10V, VOUT = 0V |
−24 |
−48 |
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mA |
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TA = 25°C (Note 2) |
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ISINK |
Output Sink Current |
VCC = 5V, VOUT = VCC |
6 |
12 |
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mA |
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(N-Channel) |
TA = 25°C (Note 2) |
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ISINK |
Output Sink Current |
VCC = 10V, VOUT = VCC |
24 |
48 |
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mA |
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(N-Channel) |
TA = 25°C (Note 2) |
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Note 2: These are peak output current capabilities. Continuous output current is rated at 12 mA max.
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4 |
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