October 1987
Revised January 1999
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS) transistors to achieve wide power supply operating range, low power consumption and high noise margin these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND.
Features
■Wide supply voltage range: 3.0V to 15V
■Guaranteed noise margin: 1.0V
■High noise immunity: 0.45 VCC (typ.)
■Low power: TTL compatibility: Fan out of 2 driving 74L
■Low power consumption: 10 nW/package (typ.)
■The MM74C86 follows the MM74LS86 Pinout
Ordering Code:
Order Number |
Package Number |
Package Description |
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MM74C86M |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
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MM74C86N |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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Pin Assignments for DIP and SOIC |
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Inputs |
Output |
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A |
B |
Y |
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L |
L |
L |
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L |
H |
H |
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H |
L |
H |
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H |
H |
L |
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H = HIGH Level
L = LOW Level
Top View
Gate OR-EXCLUSIVE Input-2 Quad MM74C86
© 1999 Fairchild Semiconductor Corporation |
DS005887.prf |
www.fairchildsemi.com |
MM74C86
Absolute Maximum Ratings(Note 1)
Voltage at any Pin (Note 1) |
−0.3V to VCC + 0.3V |
Operating Temperature Range |
−40°C to +85°C |
Storage Temperature Range |
−65°C to +150°C |
Power Dissipation (PD) |
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Dual-In-Line Package |
700 mW |
Small Outline |
500 mW |
Operating Range (VCC) |
3.0V to 15V |
Absolute Maximum (VCC) |
18V |
Lead Temperature |
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(Soldering, 10 seconds) |
260°C |
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation.
DC Electrical Characteristics
Min/max limits apply across temperature range unless otherwise noted
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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CMOS TO CMOS |
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VIN(1) |
Logical “1” Input Voltage |
VCC = 5.0V |
3.5 |
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V |
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VCC = 10V |
8.0 |
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V |
VIN(0) |
Logical “0” Input Voltage |
VCC = 5.0V |
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1.5 |
V |
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VCC = 10V |
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2.0 |
V |
VOUT(1) |
Logical “1” Output Voltage |
VCC = 5.0V, IO = −10 μA |
4.5 |
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V |
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VCC = 10V, IO = −10 μA |
9.0 |
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V |
VOUT(0) |
Logical “0” Output Voltage |
VCC = 5.0V, IO = +10 μA |
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0.5 |
V |
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VCC = 10V, IO = +10 μA |
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1.0 |
V |
IIN(1) |
Logical “1” Input Current |
VCC = 15V, VIN = 15V |
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0.005 |
1.0 |
μA |
IIN(0) |
Logical “0” Input Current |
VCC = 15V, VIN = 0V |
−1.0 |
−0.005 |
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μA |
ICC |
Supply Current |
VCC = 15V |
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0.01 |
15 |
μA |
CMOS/LPTTL INTERFACE |
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VIN(1) |
Logical “1” Input Voltage |
VCC = 4.75V |
VCC−1.5 |
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V |
VIN(0) |
Logical “0” Input Voltage |
VCC = 4.75V |
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0.8 |
V |
VOUT(1) |
Logical “1” Output Voltage |
VCC = 4.75V, IO = −360 μA |
2.4 |
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V |
VOUT(0) |
Logical “0” Output Voltage |
VCC = 4.75V, IO = 360 μA |
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0.4 |
V |
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) |
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ISOURCE |
Output Source Current |
VCC = 5.0V, VOUT = 0V |
−1.75 |
−3.3 |
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mA |
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(P-Channel) |
TA = 25°C |
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ISOURCE |
Output Source Current |
VCC = 10V, VOUT = 0V |
−8.0 |
−15 |
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mA |
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(P-Channel) |
TA = 25°C |
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ISINK |
Output Sink Current |
VCC = 5.0V, VOUT = VCC |
1.75 |
3.6 |
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mA |
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(N-Channel) |
TA = 25°C |
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ISINK |
Output Sink Current |
VCC = 10V, VOUT = VCC |
8.0 |
16 |
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mA |
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(N-Channel) |
TA = 25°C |
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AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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tpd |
Propagation Time to Logical |
VCC = 5.0V |
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110 |
185 |
ns |
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“1” or “0” |
V CC = 10V |
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50 |
90 |
ns |
CIN |
Input Capacitance |
(Note 3) |
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5.0 |
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pF |
CPD |
Power Dissipation Capacitance |
Per Gate (Note 4) |
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20 |
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pF |
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note— AN-90.
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