Analog Devices ADSP-2164KP-40, ADSP-2164BS-40, ADSP-2164BP-40, ADSP-2163KS-66, ADSP-2163KS-100 Datasheet

a		ADSP-2100 Family
		DSP Microcomputers
		ADSP-21xx

SUMMARY

16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory

Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses

Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter

Single-Cycle Instruction Execution & Multifunction Instructions

On-Chip Program Memory RAM or ROM & Data Memory RAM

Integrated I/O Peripherals: Serial Ports, Timer, Host Interface Port (ADSP-2111 Only)

FEATURES

25 MIPS, 40 ns Maximum Instruction Rate

Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data

(Three-Bus Performance)

Dual Data Address Generators with Modulo and Bit-Reverse Addressing

Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup

Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e.g., EPROM )

Double-Buffered Serial Ports with Companding Hardware, Automatic Data Buffering, and Multichannel Operation ADSP-2111 Host Interface Port Provides Easy Interface

to 68000, 80C51, ADSP-21xx, Etc.

Automatic Booting of ADSP-2111 Program Memory Through Host Interface Port

Three Edgeor Level-Sensitive Interrupts Low Power IDLE Instruction

PGA, PLCC, PQFP, and TQFP Packages MIL-STD-883B Versions Available

GENERAL DESCRIPTION

The ADSP-2100 Family processors are single-chip microcomputers optimized for digital signal processing (DSP) and other high speed numeric processing applications. The

ADSP-21xx processors are all built upon a common core. Each processor combines the core DSP architecture—computation units, data address generators, and program sequencer—with differentiating features such as on-chip program and data memory RAM, a programmable timer, one or two serial ports, and, on the ADSP-2111, a host interface port.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

	FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS		MEMORY			FLAGS
	PROGRAM			DATA	(ADSP-2111)
GENERATORS		PROGRAM
DAG 1 DAG 2	SEQUENCER	MEMORY	MEMORY
					EXTERNAL
					ADDRESS
	PROGRAM MEMORY ADDRESS				BUS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

			EXTERNAL
			DATA
			BUS
ARITHMETIC UNITS	SERIAL PORTS	TIMER	HOST
			INTERFACE
ALU MAC SHIFTER	SPORT 0 SPORT 1		PORT
			(ADSP-2111)

ADSP-2100 CORE

This data sheet describes the following ADSP-2100 Family processors:

ADSP-2101
ADSP-2103	3.3 V Version of ADSP-2101
ADSP-2105	Low Cost DSP
ADSP-2111	DSP with Host Interface Port
ADSP-2115
ADSP-2161/62/63/64	Custom ROM-programmed DSPs

The following ADSP-2100 Family processors are not included in this data sheet:

ADSP-2100A

DSP Microprocessor

ADSP-2165/66 ROM-programmed ADSP-216x processors with powerdown and larger on-chip memories (12K Program Memory ROM, 1K Program Memory RAM, 4K Data Memory RAM)

ADSP-21msp5x Mixed-Signal DSP Processors with integrated on-chip A/D and D/A plus powerdown

ADSP-2171	Speed and feature enhanced ADSP-2100
	Family processor with host interface port,
	powerdown, and instruction set extensions
	for bit manipulation, multiplication, biased
	rounding, and global interrupt masking
ADSP-2181	ADSP-21xx processor with ADSP-2171
	features plus 80K bytes of on-chip RAM
	configured as 16K words of program
	memory and 16K words of data memory.

Refer to the individual data sheet of each of these processors for further information.

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] Fax: [phone]

ADSP-21xx

Fabricated in a high speed, submicron, double-layer metal CMOS process, the highest-performance ADSP-21xx processors operate at 25 MHz with a 40 ns instruction cycle time. Every instruction can execute in a single cycle. Fabrication in CMOS results in low power dissipation.

The ADSP-2100 Family’s flexible architecture and comprehensive instruction set support a high degree of parallelism. In one cycle the ADSP-21xx can perform all of the following operations:

•Generate the next program address

•Fetch the next instruction

•Perform one or two data moves

•Update one or two data address pointers

•Perform a computation

•Receive and transmit data via one or two serial ports

•Receive and/or transmit data via the host interface port (ADSP-2111 only)

The ADSP-2101, ADSP-2105, and ADSP-2115 comprise the basic set of processors of the family. Each of these three devices contains program and data memory RAM, an interval timer, and one or two serial ports. The ADSP-2103 is a 3.3 volt power supply version of the ADSP-2101; it is identical to the ADSP-2101 in all other characteristics. Table I shows the features of each ADSP-21xx processor.

The ADSP-2111 adds a 16-bit host interface port (HIP) to the basic set of ADSP-21xx integrated features. The host port provides a simple interface to host microprocessors or microcontrollers such as the 8031, 68000, or ISA bus.

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1

Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . . 6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 10 Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . 13 ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering Procedure for ADSP-216x ROM Processors . . . . 13 Wafer Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional Differences for Older Revision Devices . . . . . . 14 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPECIFICATIONS

(ADSP-2101/2105/2115/2161/2163) . . . . . . . . . . . . . . . 17 Recommended Operating Conditions . . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Supply Current & Power (ADSP-2101/2161/2163) . . . . . . 18 Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 19 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 19 Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SPECIFICATIONS

(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Recommended Operating Conditions . . . . . . . . . . . . . . . . 21 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 23 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 23

Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SPECIFICATIONS (ADSP-2103/2162/2164) . . . . . . . . . 25

Recommended Operating Conditions . . . . . . . . . . . . . . . . 25

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 27

Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 27

Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163) . . . . . . . . . . . . 29

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . 36

TIMING PARAMETERS (ADSP-2103/2162/2164) . . . . 44

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PIN CONFIGURATIONS

68-Pin PGA (ADSP-2101) . . . . . . . . . . . . . . . . . . . . . . . . 51

68-Lead PLCC (ADSP-2101/2103/2105/2115/216x) . . . . 52

80-Lead PQFP (ADSP-2101/2103/2115/216x) . . . . . . . . . 53

80-Lead TQFP (ADSP-2115) . . . . . . . . . . . . . . . . . . . . . . 53

100-Pin PGA (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . 54

100-Lead PQFP (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . 55

PACKAGE OUTLINE DIMENSIONS

68-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

80-Lead PQFP, 80-Lead TQFP . . . . . . . . . . . . . . . . . . . . 58

100-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

100-Lead PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . 61-62

–2–

REV. B

ADSP-21xx

Table I. ADSP-21xx Processor Features

Feature

2101

2103

2105

2115

2111

Data Memory (RAM)

1K

1K

1⁄2 K

1⁄2 K

1K

Program Memory (RAM)

2K

2K

1K

1K

2K

Timer

•

•

•

•

•

Serial Port 0 (Multichannel)

•

•

–

•

•

Serial Port 1

•

•

•

•

•

Host Interface Port

–

–

–

–

•

Speed Grades (Instruction Cycle Time)

•

10.24 MHz (76.9 ns)

–

–

–

–

13.0 MHz (76.9 ns)

–

–

–

–

•

13.824 MHz (72.3 ns)

–

–

•

–

–

16.67 MHz (60 ns)

•

–

–

•

•

20.0 MHz (50 ns)

•

–

•

•

•

25 MHz (40 ns)

•

–

–

•

–

Supply Voltage

5 V

3.3 V

5 V

5 V

5 V

Packages

•

68-Pin PGA

–

–

–

–

•

68-Lead PLCC

•

•

•

–

80-Lead PQFP

•

•

–

•

–

80-Lead TQFP

–

–

–

•

–

100-Pin PGA

–

–

–

–

•

100-Lead PQFP

–

–

–

–

•

Temperature Grades

•

•

•

•

•

K Commercial

0°C to +70°C

•

•

•

•

•

B Industrial –40°C to +85°C

T Extended

–55°C to +125°C

•

–

–

–

•

Table II. ADSP-216x ROM-Programmed Processor Features

Feature

2161

2162

2163

2164

Data Memory (RAM)

1⁄2 K

1⁄2 K

1⁄2 K

1⁄2 K

Program Memory (ROM)

8K

8K

4K

4K

Program Memory (RAM)

–

–

–

–

Timer

•

•

•

•

Serial Port 0 (Multichannel)

•

•

•

•

•

•

•

•

Serial Port 1

Supply Voltage

5 V

3.3 V

5 V

3.3 V

Speed Grades (Instruction Cycle Time)

•

•

10.24 MHz (97.6 ns)

–

–

16.67 MHz (60 ns)

•

–

•

–

25 MHz (40 ns)

–

–

•

–

Packages

•

•

•

•

68-Lead PLCC

•

•

•

•

80-Lead PQFP

Temperature Grades

•

•

•

•

K Commercial

0°C to +70°C

•

•

•

•

B Industrial

–40°C to +85°C

REV. B

–3–

ADSP-21xx

The ADSP-216x series are memory-variant versions of the ADSP-2101 and ADSP-2103 that contain factory-programmed on-chip ROM program memory. These devices offer different amounts of on-chip memory for program and data storage. Table II shows the features available in the ADSP-216x series of custom ROM-coded processors.

The ADSP-216x products eliminate the need for an external boot EPROM in your system, and can also eliminate the need for any external program memory by fitting the entire application program in on-chip ROM. These devices thus provide an excellent option for volume applications where board space and system cost constraints are of critical concern.

Development Tools

The ADSP-21xx processors are supported by a complete set of tools for system development. The ADSP-2100 Family Development Software includes C and assembly language tools that allow programmers to write code for any of the ADSP-21xx processors. The ANSI C compiler generates ADSP-21xx assembly source code, while the runtime C library provides ANSI-standard and custom DSP library routines. The ADSP21xx assembler produces object code modules which the linker combines into an executable file. The processor simulators provide an interactive instruction-level simulation with a reconfigurable, windowed user interface. A PROM splitter utility generates PROM programmer compatible files.

EZ-ICE® in-circuit emulators allow debugging of ADSP-21xx systems by providing a full range of emulation functions such as modification of memory and register values and execution breakpoints. EZ-LAB® demonstration boards are complete DSP systems that execute EPROM-based programs.

The EZ-Kit Lite is a very low-cost evaluation/development platform that contains both the hardware and software needed to evaluate the ADSP-21xx architecture.

Additional details and ordering information is available in the

ADSP-2100 Family Software & Hardware Development Tools data sheet (ADDS-21xx-TOOLS). This data sheet can be requested from any Analog Devices sales office or distributor.

Additional Information

This data sheet provides a general overview of ADSP-21xx processor functionality. For detailed design information on the architecture and instruction set, refer to the ADSP-2100 Family User’s Manual, available from Analog Devices.

ARCHITECTURE OVERVIEW

Figure 1 shows a block diagram of the ADSP-21xx architecture. The processors contain three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter.

The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword floating-point representations.

The internal result (R) bus directly connects the computational units so that the output of any unit may be used as the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address generators ensure efficient use of these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-21xx executes looped code with zero overhead—no explicit jump instructions are required to maintain the loop.

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. The circular buffering feature is also used by the serial ports for automatic data transfers to (and from) onchip memory.

Efficient data transfer is achieved with the use of five internal buses:

•Program Memory Address (PMA) Bus

•Program Memory Data (PMD) Bus

•Data Memory Address (DMA) Bus

•Data Memory Data (DMD) Bus

•Result (R) Bus

The two address buses (PMA, DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD, DMD) share a single external data bus. The BMS, DMS, and PMS signals indicate which memory space is using the external buses.

Program memory can store both instructions and data, permitting the ADSP-21xx to fetch two operands in a single cycle, one from program memory and one from data memory. The processor can fetch an operand from on-chip program memory and the next instruction in the same cycle.

The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation. External devices can gain control of the processor’s buses with the use of the bus request/grant signals (BR, BG).

EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.

–4–

REV. B

									ADSP-21xx
				INSTRUCTION	PROGRAM	DATA			FLAGS
				REGISTER	MEMORY	MEMORY			(ADSP-2111 Only)	3
DATA		DATA			SRAM	SRAM		BOOT
								ADDRESS	TIMER
ADDRESS		ADDRESS		PROGRAM	or ROM			GENERATOR
GENERATOR	GENERATOR
				SEQUENCER
#1		#2
		14	PMA BUS		24		16	PMA BUS
										14	EXTERNAL
		14	DMA BUS					DMA BUS	MUX		ADDRESS
											BUS
	24	PMD BUS						PMD BUS
				BUS						24	EXTERNAL
				EXCHANGE					MUX		DATA
	16	DMD BUS						DMD BUS			BUS
INPUT REGS		INPUT REGS		INPUT REGS			COMPANDING		HOST		11
								CIRCUITRY	PORT
ALU			MAC	SHIFTER	TRANSMIT REG			TRANSMIT REG	CONTROL		EXTERNAL
OUTPUT REGS		OUTPUT REGS		OUTPUT REGS	RECEIVE REG			RECEIVE REG			HOST PORT
									HOST		16 BUS
				16		SERIAL		SERIAL
						PORT 0			PORT
								PORT 1	DATA
					(Not on ADSP-2105)
				R Bus					HOST INTERFACE PORT
						5		5
									(ADSP-2111 Only)

Figure 1. ADSP-21xx Block Diagram

One bus grant execution mode (GO Mode) allows the ADSP21xx to continue running from internal memory. A second execution mode requires the processor to halt while buses are granted.

Each ADSP-21xx processor can respond to several different interrupts. There can be up to three external interrupts, configured as edgeor level-sensitive. Internal interrupts can be generated by the timer, serial ports, and, on the ADSP-2111, the host interface port. There is also a master RESET signal.

Booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. After reset, three wait states are automatically generated. This allows, for example, a 60 ns ADSP-2101 to use a 200 ns EPROM as external boot memory. Multiple programs can be selected and loaded from the EPROM with no additional hardware.

The data receive and transmit pins on SPORT1 (Serial Port 1) can be alternatively configured as a general-purpose input flag and output flag. You can use these pins for event signalling to and from an external device. The ADSP-2111 has three additional flag outputs whose states are controlled through software.

A programmable interval timer can generate periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n cycles, where n–1 is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-21xx processors include two synchronous serial ports (“SPORTs”) for serial communications and multiprocessor communication. All of the ADSP-21xx processors have two serial ports (SPORT0, SPORT1) except for the ADSP-2105, which has only SPORT1.

The serial ports provide a complete synchronous serial interface with optional companding in hardware. A wide variety of framed or frameless data transmit and receive modes of operation are available. Each SPORT can generate an internal programmable serial clock or accept an external serial clock.

Each serial port has a 5-pin interface consisting of the following signals:

Signal Name	Function
SCLK	Serial Clock (I/O)
RFS	Receive Frame Synchronization (I/O)
TFS	Transmit Frame Synchronization (I/O)
DR	Serial Data Receive
DT	Serial Data Transmit

The ADSP-21xx serial ports offer the following capabilities:

Bidirectional—Each SPORT has a separate, double-buffered transmit and receive function.

Flexible Clocking—Each SPORT can use an external serial clock or generate its own clock internally.

REV. B

–5–

ADSP-21xx

Flexible Framing—The SPORTs have independent framing for the transmit and receive functions; each function can run in a frameless mode or with frame synchronization signals internally generated or externally generated; frame sync signals may be active high or inverted, with either of two pulse widths and timings.

Different Word Lengths—Each SPORT supports serial data word lengths from 3 to 16 bits.

Companding in Hardware—Each SPORT provides optional A-law and μ-law companding according to CCITT recommendation G.711.

Flexible Interrupt Scheme—Receive and transmit functions can generate a unique interrupt upon completion of a data word transfer.

Autobuffering with Single-Cycle Overhead—Each SPORT can automatically receive or transmit the contents of an entire circular data buffer with only one overhead cycle per data word; an interrupt is generated after the transfer of the entire buffer is completed.

Multichannel Capability (SPORT0 Only)—SPORT0 provides a multichannel interface to selectively receive or transmit a 24-word or 32-word, time-division multiplexed serial bit stream; this feature is especially useful for T1 or CEPT interfaces, or as a network communication scheme for multiple processors. (Note that the ADSP-2105 includes only SPORT1, not SPORT0, and thus does not offer multichannel operation.)

Alternate Configuration—SPORT1 can be alternatively configured as two external interrupt inputs (IRQ0, IRQ1) and the Flag In and Flag Out signals (FI, FO).

Host Interface Port (ADSP-2111)

The ADSP-2111 includes a Host Interface Port (HIP), a parallel I/O port that allows easy connection to a host processor. Through the HIP, the ADSP-2111 can be accessed by the host processor as a memory-mapped peripheral. The host interface port can be thought of as an area of dual-ported memory, or mailbox registers, that allows communication between the computational core of the ADSP-2111 and the host computer. The host interface port is completely asynchronous. The host processor can write data into the HIP while the ADSP-2111 is operating at full speed.

Three pins configure the HIP for operation with different types of host processors. The HSIZE pin configures HIP for 8- or 16bit communication with the host processor. HMD0 configures the bus strobes, selecting either separate read and write strobes or a single read/write select and a host data strobe. HMD1 selects either separate address (3-bit) and data (16-bit) buses or a multiplexed 16-bit address/data bus with address latch enable. Tying these pins to appropriate values configures the ADSP2111 for straight-wire interface to a variety of industry-standard microprocessors and microcomputers.

The HIP contains six data registers (HDR5-0) and two status registers (HSR7-6) with an associated HMASK register for masking interrupts from individual HIP data registers. The HIP data registers are memory-mapped in the internal data memory

of the ADSP-2111. The two status registers provide status information to both the ADSP-2111 and the host processor. HSR7 contains a software reset bit which can be set by both the ADSP-2111 and the host.

HIP transfers can be managed using either interrupts or polling. The HIP generates an interrupt whenever an HDR register receives data from a host processor write. It also generates an interrupt when the host processor has performed a successful read of any HDR. The read/write status of the HDRs is also stored in the HSR registers.

The HMASK register bits can be used to mask the generation of read or write interrupts from individual HDR registers. Bits in the IMASK register enable and disable all HIP read interrupts or all HIP write interrupts. So, for example, a write to HDR4 will cause an interrupt only if both the HDR4 Write bit in HMASK and the HIP Write interrupt enable bit in IMASK are set.

The HIP provides a second method of booting the ADSP-2111 in which the host processor loads instructions into the HIP. The ADSP-2111 automatically transfers the data, in this case opcodes, to internal program memory. The BMODE pin determines whether the ADSP-2111 boots from the host processor through the HIP or from external EPROM over the data bus.

Interrupts

The ADSP-21xx’s interrupt controller lets the processor respond to interrupts with a minimum of overhead. Up to three external interrupt input pins, IRQ0, IRQ1, and IRQ2, are provided. IRQ2 is always available as a dedicated pin; IRQ1 and IRQ0 may be alternately configured as part of Serial Port 1. The ADSP-21xx also supports internal interrupts from the timer, the serial ports, and the host interface port (on the ADSP-2111). The interrupts are internally prioritized and individually maskable (except for RESET which is non-maskable). The IRQx input pins can be programmed for either levelor edgesensitivity. The interrupt priorities for each ADSP-21xx processor are shown in Table III.

The ADSP-21xx uses a vectored interrupt scheme: when an interrupt is acknowledged, the processor shifts program control to the interrupt vector address corresponding to the interrupt received. Interrupts can be optionally nested so that a higher priority interrupt can preempt the currently executing interrupt service routine. Each interrupt vector location is four instructions in length so that simple service routines can be coded entirely in this space. Longer service routines require an additional JUMP or CALL instruction.

Individual interrupt requests are logically ANDed with the bits in the IMASK register; the highest-priority unmasked interrupt is then selected.

The interrupt control register, ICNTL, allows the external interrupts to be set as either edgeor level-sensitive. Depending on bit 4 in ICNTL, interrupt service routines can either be nested (with higher priority interrupts taking precedence) or be processed sequentially (with only one interrupt service active at a time).

–6–

REV. B

ADSP-21xx

The interrupt force and clear register, IFC, is a write-only register that contains a force bit and a clear bit for each interrupt (except for level-sensitive interrupts and the ADSP-2111 HIP interrupts—these cannot be forced or cleared in software).

When responding to an interrupt, the ASTAT, MSTAT, and IMASK status registers are pushed onto the status stack and the PC counter is loaded with the appropriate vector address. The status stack is seven levels deep (nine levels deep on the ADSP-2111) to allow interrupt nesting. The stack is automatically popped when a return from the interrupt instruction is executed.

Pin Definitions

Table IV (on next page) shows pin definitions for the ADSP21xx processors. Any inputs not used must be tied to VDD.

Table III. Interrupt Vector Addresses & Priority

ADSP-2105
Interrupt									Interrupt
Source									Vector Address
		Startup							0x0000
RESET
IRQ2									0x0004 (High Priority)
SPORT1 Transmit or					IRQ1				0x0010
SPORT1 Receive or			IRQ0						0x0014
Timer									0x0018 (Low Priority)
ADSP-2101/2103/2115/216x
Interrupt									Interrupt
Source									Vector Address
		Startup							0x0000
RESET
IRQ2									0x0004 (High Priority)
SPORT0 Transmit									0x0008
SPORT0 Receive									0x000C
SPORT1 Transmit or					IRQ1				0x0010
SPORT1 Receive or				IRQ0					0x0014
Timer									0x0018 (Low Priority)
ADSP-2111
Interrupt									Interrupt
Source									Vector Address
		Startup							0x0000
RESET
IRQ2									0x0004 (High Priority)
HIP Write from Host									0x0008
HIP Read to Host									0x000C
SPORT0 Transmit									0x0010
SPORT0 Receive									0x0014
SPORT1 Transmit or					IRQ1				0x0018
SPORT1 Receive or IRQ0									0x001C
Timer									0x0020 (Low Priority)

SYSTEM INTERFACE

Figure 3 shows a typical system for the ADSP-2101, ADSP2115, or ADSP-2103, with two serial I/O devices, a boot EPROM, and optional external program and data memory. A total of 15K words of data memory and 16K words of program memory is addressable for the ADSP-2101 and ADSP-2103. A total of 14.5K words of data memory and 15K words of program memory is addressable for the ADSP-2115.

Figure 4 shows a system diagram for the ADSP-2105, with one serial I/O device, a boot EPROM, and optional external program and data memory. A total of 14.5K words of data memory and 15K words of program memory is addressable for the ADSP-2105.

Figure 5 shows a system diagram for the ADSP-2111, with two serial I/O devices, a host processor, a boot EPROM, and optional external program and data memory. A total of 15K words of data memory and 16K words of program memory is addressable.

Programmable wait-state generation allows the processors to easily interface to slow external memories.

The ADSP-2101, ADSP-2103, ADSP-2115, and ADSP-2111 processors also provide either: one external interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or three external interrupts (IRQ2, IRQ1, IRQ0) and one serial port (SPORT0).

The ADSP-2105 provides either: one external interrupt (IRQ2) and one serial port (SPORT1), or three external interrupts (IRQ2, IRQ1, IRQ0) with no serial port.

Clock Signals

The ADSP-21xx processors’ CLKIN input may be driven by a crystal or by a TTL-compatible external clock signal. The CLKIN input may not be halted or changed in frequency during operation, nor operated below the specified low frequency limit.

If an external clock is used, it should be a TTL-compatible signal running at the instruction rate. The signal should be connected to the processor’s CLKIN input; in this case, the XTAL input must be left unconnected.

Because the ADSP-21xx processors include an on-chip oscillator circuit, an external crystal may also be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 2. A parallelresonant, fundamental frequency, microprocessor-grade crystal should be used.

CLKIN

XTAL

CLKOUT

ADSP-21xx

Figure 2. External Crystal Connections

REV. B

–7–

ADSP-21xx

A clock output signal (CLKOUT) is generated by the processor, synchronized to the processor’s internal cycles.

Reset

The RESET signal initiates a complete reset of the ADSP-21xx. The RESET signal must be asserted when the chip is powered up to assure proper initialization. If the RESET signal is applied during initial power-up, it must be held long enough to allow the processor’s internal clock to stabilize. If RESET is activated at any time after power-up and the input clock frequency does not change, the processor’s internal clock continues and does not require this stabilization time.

The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 tCK cycles will ensure that the PLL has locked (this does not, however, include the crystal oscillator start-up time). During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse width specification, tRSP.

To generate the RESET signal, use either an RC circuit with an external Schmidt trigger or a commercially available reset IC. (Do not use only an RC circuit.)

Table IV. ADSP-21xx Pin Definitions

Pin

# of

Input /

Name(s)

Pins

Output

Function

Address

14

O

Address outputs for program, data and boot memory.

Data1

24

I/O

Data I/O pins for program and data memories. Input only for

boot memory, with two MSBs used for boot memory addresses.

Unused data lines may be left floating.

RESET

1

I

Processor Reset Input

IRQ2

1

I

External Interrupt Request #2

BR

2

1

I

External Bus Request Input

BG

1

O

External Bus Grant Output

PMS

1

O

External Program Memory Select

DMS

1

O

External Data Memory Select

BMS

1

O

Boot Memory Select

RD

1

O

External Memory Read Enable

WR

1

O

External Memory Write Enable

MMAP

1

I

Memory Map Select Input

CLKIN, XTAL

2

I

External Clock or Quartz Crystal Input

CLKOUT

1

O

Processor Clock Output

VDD

Power Supply Pins

GND

Ground Pins

SPORT03

5

I/O

Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)

SPORT1

5

I/O

Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)

or Interrupts & Flags:

IRQ0

(RFS1)

1

I

External Interrupt Request #0

IRQ1

(TFS1)

1

I

External Interrupt Request #1

FI (DR1)

1

I

Flag Input Pin

FO (DT1)

1

O

Flag Output Pin

FL2–0 (ADSP-2111 Only)

3

O

General Purpose Flag Output Pins

Host Interface Port

(ADSP-2111 Only)

HSEL

1

I

HIP Select Input

HACK

1

O

HIP Acknowledge Output

HSIZE

1

I

8/16-Bit Host Select (0 = 16-Bit, 1 = 8-Bit)

BMODE

1

I

Boot Mode Select (0 = Standard EPROM Booting, 1 = HIP Booting)

HMD0

1

I

Bus Strobe Select (0 =

RD

/

WR

, 1 = RW/

DS

)

HMD1

1

I

HIP Address/Data Mode Select (0 = Separate, 1 = Multiplexed)

HRD

/HRW

1

I

HIP Read Strobe or Read/Write Select

HWR

/

HDS

1

I

HIP Write Strobe or Host Data Strobe Select

HD15–0/HAD15-0

16

I/O

HIP Data or HIP Data and Address

HA2/ALE

1

I

Host Address 2 Input or Address Latch Enable Input

HA1–0/Unused

2

I

Host Address 1 and 0 Inputs

NOTES

1Unused data bus lines may be left floating. 2BR must be tied high (to VDD) if not used.

3ADSP-2105 does not have SPORT0. (SPORT0 pins are No Connects on the ADSP-2105.)

–8–

REV. B

ADSP-21xx

				ADSP-2101
				or	ADSP-2103
				or	ADSP-2115		14		A13-0
						ADDR13-0					BOOT
1x CLOCK				CLKIN					D23-22	ADDR
											MEMORY
	or			XTAL
CRYSTAL							24		D15-8		e.g. EPROM
				CLKOUT		DATA23-0				DATA	2764
				RESET							27128
										OE	27256
										CS
				IRQ2		BMS					27512
				BR					A13-0
				BG						ADDR
				MMAP					D23-0	DATA	PROGRAM
											MEMORY
				SPORT 1		RD				OE
				SCLK1		WR				WE	(OPTIONAL)
	SERIAL			RFS1 or IRQ0						CS
	DEVICE			TFS1 or IRQ1					A13-0
	(OPTIONAL)			DT1 or	FO
										ADDR	DATA
				DR1 or	FI
									D23-8
				SPORT 0						DATA	MEMORY
											&
	SERIAL			SCLK0		PMS				OE	PERIPHERALS
				RFS0						WE
	DEVICE			TFS0
						DMS					(OPTIONAL)
	(OPTIONAL)			DT0						CS
				DR0

THE TWO MSBs OF THE DATA BUS (D23-22 ) ARE USED TO SUPPLY THE TWO MSBs OF THE

BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.

Figure 3. ADSP-2101/ADSP-2103/ADSP-2115 System

				ADSP-2105
									A13-0
						ADDR13-0	14
											BOOT
1x CLOCK				CLKIN					D23-22	ADDR
											MEMORY
	or			XTAL
CRYSTAL							24		D15-8		e.g. EPROM
				CLKOUT		DATA23-0				DATA	2764
				RESET							27128
										OE	27256
				IRQ2						CS
						BMS					27512
				BR					A13-0
				BG						ADDR
				MMAP					D23-0	DATA	PROGRAM
											MEMORY
				SPORT 1		RD				OE
				SCLK1		WR				WE	(OPTIONAL)
	SERIAL			RFS1 or IRQ0						CS
	DEVICE			TFS1 or	IRQ1				A13-0
	(OPTIONAL)			DT1 or	FO
										ADDR	DATA
				DR1 or	FI
									D23-8
										DATA	MEMORY
						PMS					&
										OE	PERIPHERALS
										WE
						DMS				CS	(OPTIONAL)

THE TWO MSBs OF THE DATA BUS (D23-22 ) ARE USED TO SUPPLY THE TWO MSBs OF THE

BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.

Figure 4. ADSP-2105 System

REV. B

–9–

ADSP-21xx

ADSP-2111

A13-0

14

BOOT

ADDR13-0

1x CLOCK

CLKIN

D23-22

ADDR

MEMORY

(OPTIONAL)

or

XTAL

CRYSTAL

24

D15-8

e.g. EPROM

CLKOUT

DATA23-0

DATA

2764

RESET

27128

OE

27256

IRQ2

BMS

CS

27512

BR

A13-0

BG

ADDR

MMAP

D23-0

DATA

PROGRAM

MEMORY

SPORT 1

RD

OE

SCLK1

WR

WE

(OPTIONAL)

SERIAL

RFS1 or IRQ0

CS

DEVICE

TFS1 or

IRQ1

A13-0

(OPTIONAL)

DT1 or

FO

ADDR

DATA

DR1 or

FI

D23-8

SPORT 0

DATA

MEMORY

&

SERIAL

SCLK0

PMS

OE

PERIPHERALS

RFS0

WE

DEVICE

TFS0

(OPTIONAL)

(OPTIONAL)

DT0

DMS

CS

DR0

FL0

FL1

FL2

HOST

HOST INTERFACE PORT

PROCESSOR

7

(OPTIONAL)

CONTROL

DATA / ADDR

16

THE TWO MSBs OF THE DATA BUS (D23-22 ) ARE USED TO SUPPLY THE TWO MSBs OF THE

BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.

Figure 5. ADSP-2111 System

The RESET input resets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, the boot loading sequence is performed (provided there is no pending bus request and the chip is configured for booting, with MMAP = 0). The first instruction is then fetched from internal program memory location 0x0000.

Program Memory Interface

The on-chip program memory address bus (PMA) and on-chip program memory data bus (PMD) are multiplexed with the onchip data memory buses (DMA, DMD), creating a single external data bus and a single external address bus. The external data bus is bidirectional and is 24 bits wide to allow instruction fetches from external program memory. Program memory may contain code and data.

The external address bus is 14 bits wide. For the ADSP-2101, ADSP-2103, and ADSP-2111, these lines can directly address up to 16K words, of which 2K are on-chip. For the ADSP-2105 and ADSP-2115, the address lines can directly address up to 15K words, of which 1K is on-chip.

The data lines are bidirectional. The program memory select (PMS) signal indicates accesses to program memory and can be used as a chip select signal. The write (WR) signal indicates a write operation and is used as a write strobe. The read (RD) signal indicates a read operation and is used as a read strobe or output enable signal.

The ADSP-21xx processors write data from their 16-bit registers to 24-bit program memory using the PX register to provide the lower eight bits. When the processor reads 16-bit data from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the PX register.

The program memory interface can generate 0 to 7 wait states for external memory devices; default is to 7 wait states after

RESET.

Program Memory Maps

Program memory can be mapped in two ways, depending on the state of the MMAP pin. Figure 6 shows the two program memory maps for the ADSP-2101, ADSP-2103, and ADSP-2111. Figure 8 shows the program memory maps for the ADSP-2105 and ADSP-2115. Figures 7 and 9 show the program memory maps for the ADSP-2161/62 and ADSP-2163/ 64, respectively.

–10–

REV. B

ADSP-21xx

ADSP-2101/ADSP-2103/ADSP-2111

When MMAP = 0, on-chip program memory RAM occupies 2K words beginning at address 0x0000. Off-chip program memory uses the remaining 14K words beginning at address 0x0800. In this configuration–when MMAP = 0–the boot loading sequence (described below in “Boot Memory Interface”) is automatically initiated when RESET is released.

When MMAP = 1, 14K words of off-chip program memory begin at address 0x0000 and on-chip program memory RAM is located in the upper 2K words, beginning at address 0x3800. In this configuration, program memory is not booted although it can be written to and read under program control.

ADSP-2105/ADSP-2115

When MMAP = 0, on-chip program memory RAM occupies 1K words beginning at address 0x0000. Off-chip program memory uses the remaining 14K words beginning at address 0x0800. In this configuration–when MMAP = 0–the boot loading sequence (described below in “Boot Memory Interface”) is automatically initiated when RESET is released.

When MMAP = 1, 14K words of off-chip program memory begin at address 0x0000 and on-chip program memory RAM is located in the 1K words between addresses 0x3800–0x3BFF. In this configuration, program memory is not booted although it can be written to and read under program control.

	0x0000		0x0000
INTERNAL
RAM
2K
LOADED FROM
EXTERNAL
BOOT MEMORY	0x07FF
	0x0800	EXTERNAL
		14K
EXTERNAL
14K			0x37FF
			0x3800
		INTERNAL
		RAM
		2K
	0x3FFF		0x3FFF
MMAP=0		MMAP=1

No Booting

Figure 6. ADSP-2101/ADSP-2103/ADSP-2111 Program

Memory Maps

		0x0000	2K	0x0000
	8K		EXTERNAL
				0x07FF
	INTERNAL
				0x0800
	ROM
			6K
			INTERNAL
			ROM
		0x1FF0		0x1FF0
	RESERVED		RESERVED
				0x1FFF
		0x1FFF
				0x2000
		0x2000
			6K
			EXTERNAL
	8K
	EXTERNAL
				0x37FF
				0x3800
			2K
			INTERNAL
			ROM
		0x3FFF		0x3FFF
	MMAP=0		MMAP=1

Figure 7. ADSP-2161/62 Program Memory Maps

	0x0000		0x0000
INTERNAL RAM
1K
LOADED FROM
EXTERNAL
BOOT MEMORY	0x03FF
	0x0400	EXTERNAL
RESERVED		14K
1K
	0x07FF
	0x0800
			0x37FF
			0x3800
EXTERNAL		INTERNAL RAM
		1K
14K
			0x3BFF
			0x3C00
		RESERVED
		1K
	0x3FFF		0x3FFF
MMAP=0		MMAP=1

No Booting

Figure 8. ADSP-2105/ADSP-2115 Program Memory Maps

		0x0000		0x0000
			2K
	4K		EXTERNAL
				0x07FF
	INTERNAL
	ROM		2K	0x0800
			INTERNAL
			ROM
		0x0FF0		0x0FF0
	RESERVED		RESERVED
		0x0FFF		0x0FFF
		0x1000		0x1000
			10K
	12K		EXTERNAL
	EXTERNAL
				0x37FF
				0x3800
			2K
			INTERNAL
			ROM
		0x3FFF		0x3FFF
	MMAP=0		MMAP=1

Figure 9. ADSP-2163/64 Program Memory Maps

REV. B

–11–

ADSP-21xx

Data Memory Interface

The data memory address bus (DMA) is 14 bits wide. The bidirectional external data bus is 24 bits wide, with the upper 16 bits used for data memory data (DMD) transfers.

The data memory select (DMS) signal indicates access to data memory and can be used as a chip select signal. The write (WR) signal indicates a write operation and can be used as a write strobe. The read (RD) signal indicates a read operation and can be used as a read strobe or output enable signal.

The ADSP-21xx processors support memory-mapped I/O, with the peripherals memory-mapped into the data memory address space and accessed by the processor in the same manner as data memory.

Data Memory Map ADSP-2101/ADSP-2103/ADSP-2111

For the ADSP-2101, ADSP-2103, and ADSP-2111, on-chip data memory RAM resides in the 1K words beginning at address 0x3800, as shown in Figure 10. Data memory locations from 0x3C00 to the end of data memory at 0x3FFF are reserved. Control and status registers for the system, timer, wait-state configuration, and serial port operations are located in this region of memory.

ADSP-2105/ADSP-2115

For the ADSP-2105 and ADSP-2115, on-chip data memory RAM resides in the 512 words beginning at address 0x3800, also shown in Figure 10. Data memory locations from 0x3A00 to the end of data memory at 0x3FFF are reserved. Control and status registers for the system, timer, wait-state configuration, and serial port operations are located in this region of memory.

1K for ADSP-2101 ADSP-2103 ADSP-2111

1K EXTERNAL

DWAIT0

1K EXTERNAL

DWAIT1

10K EXTERNAL

DWAIT2

1K EXTERNAL

DWAIT3

1K EXTERNAL

DWAIT4

512 for ADSP-2105 ADSP-2115 ADSP-216x

MEMORY-MAPPED CONTROL REGISTERS & RESERVED

0x0000

0x0400

0x0800

EXTERNAL

RAM

0x3000

0x3400

0x3800

0x3A00

INTERNAL

RAM

0x3C00

0x3FFF

Figure 10. Data Memory Map (All Processors)

All Processors

The remaining 14K of data memory is located off-chip. This external data memory is divided into five zones, each associated with its own wait-state generator. This allows slower peripherals to be memory-mapped into data memory for which wait states are specified. By mapping peripherals into different zones, you can accommodate peripherals with different wait-state requirements. All zones default to seven wait states after RESET.

Boot Memory Interface

On the ADSP-2101, ADSP-2103, and ADSP-2111, boot memory is an external 64K by 8 space, divided into eight separate 8K by 8 pages. On the ADSP-2105 and ADSP-2115, boot memory is a 32K by 8 space, divided into eight separate 4K by 8 pages. The 8-bit bytes are automatically packed into 24-bit instruction words by each processor, for loading into onchip program memory.

Three bits in the processors’ System Control Register select which page is loaded by the boot memory interface. Another bit in the System Control Register allows the forcing of a boot loading sequence under software control. Boot loading from Page 0 after RESET is initiated automatically if MMAP = 0.

The boot memory interface can generate zero to seven wait states; it defaults to three wait states after RESET. This allows the ADSP-21xx to boot from a single low cost EPROM such as a 27C256. Program memory is booted one byte at a time and converted to 24-bit program memory words.

The BMS and RD signals are used to select and to strobe the boot memory interface. Only 8-bit data is read over the data bus, on pins D8-D15. To accommodate up to eight pages of boot memory, the two MSBs of the data bus are used in the boot memory interface as the two MSBs of the boot memory address: D23, D22, and A13 supply the boot page number.

The ADSP-2100 Family Assembler and Linker allow the creation of programs and data structures requiring multiple boot pages during execution.

The BR signal is recognized during the booting sequence. The bus is granted after loading the current byte is completed. BR during booting may be used to implement booting under control of a host processor.

Bus Interface

The ADSP-21xx processors can relinquish control of their data and address buses to an external device. When the external device requires control of the buses, it asserts the bus request signal (BR). If the ADSP-21xx is not performing an external

memory access, it responds to the active BR input in the next cycle by:

•Three-stating the data and address buses and the PMS, DMS, BMS, RD, WR output drivers,

•Asserting the bus grant (BG) signal,

•and halting program execution.

If the Go mode is set, however, the ADSP-21xx will not halt program execution until it encounters an instruction that requires an external memory access.

–12–

REV. B

ADSP-21xx

If the ADSP-21xx is performing an external memory access when the external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the cycle after the access completes (up to eight cycles later depending on the number of wait states). The instruction does not need to be completed when the bus is granted; the ADSP-21xx will grant the bus in between two memory accesses if an instruction requires more than one external memory access.

When the BR signal is released, the processor releases the BG signal, re-enables the output drivers and continues program execution from the point where it stopped.

The bus request feature operates at all times, including when the processor is booting and when RESET is active. If this feature is not used, the BR input should be tied high (to VDD).

Low Power IDLE Instruction

The IDLE instruction places the ADSP-21xx processor in low power state in which it waits for an interrupt. When an interrupt occurs, it is serviced and execution continues with instruction following IDLE. Typically this next instruction will be a JUMP back to the IDLE instruction. This implements a low-power standby loop.

The IDLE n instruction is a special version of IDLE that slows the processor’s internal clock signal to further reduce power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor, n, given in the IDLE instruction. The syntax of the instruction is:

IDLE n;

where n = 16, 32, 64, or 128.

The instruction leaves the chip in an idle state, operating at the slower rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and the timer clock, are reduced by the same ratio. Upon receipt of an enabled interrupt, the processor will stay in the IDLE state for up to a maximum of n CLKIN cycles, where n is the divisor specified in the instruction, before resuming normal operation.

When the IDLE n instruction is used, it slows the processor’s internal clock and thus its response time to incoming interrupts– the 1-cycle response time of the standard IDLE state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21xx will remain in the IDLE state for up to a maximum of n CLKIN cycles (where n = 16, 32, 64, or 128) before resuming normal operation.

When the IDLE n instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the IDLE state (a maximum of n CLKIN cycles).

ADSP-216x Prototyping

You can prototype your ADSP-216x system with either the ADSP-2101 or ADSP-2103 RAM-based processors. When code is fully developed and debugged, it can be submitted to Analog

Devices for conversion into a ADSP-216x ROM product.

The ADSP-2101 EZ-ICE emulator can be used for development of ADSP-216x systems. For the 3.3 V ADSP-2162 and ADSP-2164, a voltage converter interface board provides 3.3 V emulation.

Additional overlay memory is used for emulation of ADSP2161/62 systems. It should be noted that due to the use of offchip overlay memory to emulate the ADSP-2161/62, a performance loss may be experienced when both executing instructions and fetching program memory data from the off-chip overlay memory in the same cycle. This can be overcome by locating program memory data in on-chip memory.

Ordering Procedure for ADSP-216x ROM Processors

To place an order for a custom ROM-coded ADSP-2161, ADSP-2162, ADSP-2163, or ADSP-2164 processor, you must:

1. Complete the following forms contained in the ADSP ROM Ordering Package, available from your Analog Devices sales representative:

ADSP-216x ROM Specification Form ROM Release Agreement

ROM NRE Agreement & Minimum Quantity Order (MQO) Acceptance Agreement for Pre-Production ROM Products

2.Return the forms to Analog Devices along with two copies of the Memory Image File (.EXE file) of your ROM code. The files must be supplied on two 3.5" or 5.25" floppy disks for the IBM PC (DOS 2.01 or higher).

3.Place a purchase order with Analog Devices for non-recurring engineering changes (NRE) associated with ROM product development.

After this information is received, it is entered into Analog Devices’ ROM Manager System which assigns a custom ROM model number to the product. This model number will be branded on all prototype and production units manufactured to these specifications.

To minimize the risk of code being altered during this process, Analog Devices verifies that the .EXE files on both floppy disks are identical, and recalculates the checksums for the .EXE file entered into the ROM Manager System. The checksum data, in the form of a ROM Memory Map, a hard copy of the .EXE file, and a ROM Data Verification form are returned to you for inspection.

REV. B

–13–

ADSP-21xx

A signed ROM Verification Form and a purchase order for production units are required prior to any product being manufactured. Prototype units may be applied toward the minimum order quantity.

Upon completion of prototype manufacture, Analog Devices will ship prototype units and a delivery schedule update for production units. An invoice against your purchase order for the NRE charges is issued at this time.

There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for details. A separate order must be placed for parts of a specific package type, temperature range, and speed grade.

Functional Differences for Older Revision Devices

Older revisions of the ADSP-21xx processors have slight differences in functionality. The two differences are as follows:

•Bus Grant (BG) is asserted in the same cycle that Bus Request (BR) is recognized (i.e. when setup and hold time requirements are met for the BR input). Bus Request input is a synchronous input rather than asynchronous. (In newer revision devices, BG is asserted in the cycle after BR is recognized.)

•Only the standard IDLE instruction is available, not the clock-reducing IDLE n instruction.

To determine the revision of a particular ADSP-21xx device, inspect the marking on the device. For example, an ADSP-2101 of revision 6.0 will have the following marking:

a

ADSP-2101

KS-66 ← Package & Speed

EE/A12345-6.0 ← Lot # & Revision Code

9234 ← Date Code

The revision codes for the older versions of each ADSP-21xx device are as follows:

Processor	Old Functionality	New Functionality
ADSP-2101	Revision Code £ 5.0	Revision Code ³ 6.0
ADSP-2105	No Revision Code	Revision Code ³ 1.0
ADSP-2115	Revision Code < 1.0	Revision Code ³ 1.0
ADSP-2111	RevisionCode < 2.0	Revision Code ³ 2.0
ADSP-2103	Revision code £ 5.0	Revision code ³ 6.0

–14–

REV. B

ADSP-21xx

Instruction Set

The ADSP-21xx assembly language uses an algebraic syntax for ease of coding and readability. The sources and destinations of computations and data movements are written explicitly in each assembly statement, eliminating cryptic assembler mnemonics.

Every instruction assembles into a single 24-bit word and executes in a single cycle. The instructions encompass a wide variety of instruction types along with a high degree of

operational parallelism. There are five basic categories of instructions: data move instructions, computational instructions, multifunction instructions, program flow control instructions and miscellaneous instructions. Multifunction instructions perform one or two data moves and a computation.

The instruction set is summarized below. The ADSP-2100 Family Users Manual contains a complete reference to the instruction set.

ALU Instructions

[IF cond] AR|AF =	xop + yop	[+ C] ;	Add/Add with Carry
=	xop – yop	[+ C– 1] ;	Subtract X – Y/Subtract X – Y with Borrow
=	yop – xop	[+ C– 1] ;	Subtract Y – X/Subtract Y – X with Borrow
=	xop AND yop ;		AND
=	xop OR yop ;		OR
=	xop XOR yop ;		XOR
=	PASS xop ;		Pass, Clear
=	– xop ;		Negate
=	NOT xop ;		NOT
=	ABS xop ;		Absolute Value
=	yop + 1 ;		Increment
=	yop – 1 ;		Decrement
=	DIVS yop, xop ;		Divide
=	DIVQ xop ;

MAC Instructions

[IF cond] MR|MF =	xop * yop ;	Multiply
= MR + xop * yop ;		Multiply/Accumulate
= MR – xop * yop ;		Multiply/Subtract
=	MR ;	Transfer MR
=	0 ;	Clear
IF MV SAT MR ;		Conditional MR Saturation

Shifter Instructions

[IF cond]	SR = [SR OR] ASHIFT xop ;	Arithmetic Shift
[IF cond]	SR = [SR OR] LSHIFT xop ;	Logical Shift
	SR = [SR OR] ASHIFT xop BY <exp>;	Arithmetic Shift Immediate
	SR = [SR OR] LSHIFT xop BY <exp>;	Logical Shift Immediate
[IF cond]	SE = EXP xop ;	Derive Exponent
[IF cond]	SB = EXPADJ xop ;	Block Exponent Adjust
[IF cond]	SR = [SR OR] NORM xop ;	Normalize

Data Move Instructions

reg = reg ;	Register-to-Register Move
reg = <data> ;	Load Register Immediate
reg = DM (<addr>) ;	Data Memory Read (Direct Address)
dreg = DM (Ix , My) ;	Data Memory Read (Indirect Address)
dreg = PM (Ix , My) ;	Program Memory Read (Indirect Address)
DM (<addr>) = reg ;	Data Memory Write (Direct Address)
DM (Ix , My) = dreg ;	Data Memory Write (Indirect Address)
PM (Ix , My) = dreg ;	Program Memory Write (Indirect Address)

Multifunction Instructions

<ALU>|<MAC>|<SHIFT> , dreg = dreg ;	Computation with Register-to-Register Move
<ALU>|<MAC>|<SHIFT> , dreg = DM (Ix , My) ;	Computation with Memory Read
<ALU>|<MAC>|<SHIFT> , dreg = PM (Ix , My) ;	Computation with Memory Read
DM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;	Computation with Memory Write
PM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;	Computation with Memory Write
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;	Data & Program Memory Read
<ALU>|<MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;	ALU/MAC with Data & Program Memory Read

REV. B

–15–

ADSP-21xx

Program Flow Instructions

DO <addr> [UNTIL term] ;			Do Until Loop
[IF cond]	JUMP (Ix) ;		Jump
[IF cond] JUMP <addr>;			Call Subroutine
[IF cond]	CALL (Ix) ;
[IF cond] CALL <addr>;			Jump/Call on Flag In Pin
IF [NOT ] FLAG_IN		JUMP <addr>;
IF [NOT ] FLAG_IN		CALL <addr>;	Modify Flag Out Pin
[IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ;
[IF cond]	RTS ;		Return from Subroutine
[IF cond]	RTI ;		Return from Interrupt Service Routine
IDLE [(n)] ;			Idle

Miscellaneous Instructions

NOP ;		No Operation
MODIFY (Ix , My);		Modify Address Register
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;		Stack Control
ENA|DIS	SEC_REG [, ...] ;	Mode Control
	BIT_REV
	AV_LATCH
	AR_SAT
	M_MODE
	TIMER
	G_MODE
Notation Conventions
Ix	Index registers for indirect addressing
My	Modify registers for indirect addressing
<data>	Immediate data value
<addr>	Immediate address value
<exp>	Exponent (shift value) in shift immediate instructions (8-bit signed number)
<ALU>	Any ALU instruction (except divide)
<MAC>	Any multiply-accumulate instruction
<SHIFT>	Any shift instruction (except shift immediate)
cond	Condition code for conditional instruction
term	Termination code for DO UNTIL loop
dreg	Data register (of ALU, MAC, or Shifter)
reg	Any register (including dregs)

;A semicolon terminates the instruction

,Commas separate multiple operations of a single instruction

[	]	Optional part of instruction
[, ...]		Optional, multiple operations of an instruction
option1 | option2		List of options; choose one.

Assembly Code Example

The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared algorithm. Notice that the computations in the instructions are written like algebraic equations.

	MF=MX0* MY1 ( RND),	MX0=DM(I2,M1);	{MF=error* b eta}
	MR=MX0* MF ( RND),	AY0=PM(I6,M5);
	DO adapt UNTIL CE;
	AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:	PM(I6,M6)=AR, MR=MX0* MF (RND);
	MODIFY(I2,M3);		{Point to oldest data}
	MODIFY(I6,M7);		{Point to start of data}

–16–

REV. B

ADSP-2101/2105/2115/2161/2163–SPECIFICATIONS								ADSP-21xx
RECOMMENDED OPERATING CONDITIONS
		K Grade		B Grade		T Grade
Parameter		Min	Max	Min	Max	Min	Max		Unit
VDD	Supply Voltage	4.50	5.50	4.50	5.50	4.50	5.50		V
TAMB	Ambient Operating Temperature	0	+70	–40	+85	–55	+125		°C

See “Environmental Conditions” for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter		Test Conditions	Min	Max	Unit
VIH	Hi-Level Input Voltage3, 5	@ VDD = max	2.0		V
VIH	Hi-Level CLKIN Voltage	@ VDD = max	2.2		V
VIL	Lo-Level Input Voltage1, 3	@ VDD = min		0.8	V
VOH	Hi-Level Output Voltage2, 3, 7	@ VDD = min, IOH = –0.5 mA	2.4		V
VOL	Lo-Level Output Voltage2, 3, 7	@ VDD = min, IOH = –100 μA8	VDD – 0.3		V
		@ VDD = min, IOL = 2 mA		0.4	V
IIH	Hi-Level Input Current1	@ VDD = max, VIN = VDD max		10	μA
IIL	Lo-Level Input Current1	@ VDD = max, VIN = 0 V		10	μA
IOZH	Tristate Leakage Current4	@ VDD = max, VIN = VDD max6		10	μA
IOZL	Tristate Leakage Current4	@ VDD = max, VIN = 0 V6		10	μA
CI	Input Pin Capacitance1, 8, 9	@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C		8	pF
CO	Output Pin Capacitance4, 8, 9, 10	@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C		8	pF

NOTES

1Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105).

2Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0 (not on ADSP-2105).

3Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0 (not on ADSP-2105), RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105).

4Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0 (not on ADSP-2105), SCLK0 (not on ADSP-2105), RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105).

5Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105). 60 V on BR, CLKIN Active (to force tristate condition).

7Although specified for TTL outputs, all ADSP-21xx outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 8Guaranteed but not tested.

9Applies to PGA, PLCC, PQFP package types.

10Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . .	. . . . . . –0.3 V to +7	V
Input Voltage . . . . . . . . . . . . . . . . . . . . .	–0.3 V to VDD + 0.3	V
Output Voltage Swing . . . . . . . . . . . . . .	–0.3 V to VDD + 0.3	V
Operating Temperature Range (Ambient)	. . . –55ºC to +125ºC
Storage Temperature Range . . . . . . . . .	. . . . –65ºC to +150ºC
Lead Temperature (10 sec) PGA . . . . . . .	. . . . . . . . . . +300ºC

Lead Temperature (5 sec) PLCC, PQFP, TQFP . . . . +280ºC

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21xx processors feature proprietary ESD protection circuitry to dissipate high energy electrostatic discharges (Human Body Model), permanent damage may occur to devices subjected to such discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before the devices are removed. Per method 3015 of MIL-STD-883, the ADSP-21xx processors have been classified as Class 1 devices.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–17–

ADSP-21xx

SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)

SUPPLY CURRENT & POWER (ADSP-2101/2105/2115/2161/2163)

Parameter		Test Conditions	Min	Max	Unit
IDD	Supply Current (Dynamic)1	@ VDD = max, tCK = 40 ns2		38	mA
		@ VDD = max, tCK = 50 ns2		31	mA
		@ VDD = max, tCK = 72.3 ns2		24	mA
IDD	Supply Current (Idle)1, 3	@ VDD = max, tCK = 40 ns4		12	mA
		@ VDD = max, tCK = 50 ns		11	mA
		@ VDD = max, tCK = 72.3 ns		10	mA

NOTES

1Current reflects device operating with no output loads.

2VIN = 0.4 V and 2.4 V.

3Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 4ADSP-2105 is not available in a 25 MHz speed grade.

For typical supply current (internal power dissipation) figures, see Figure 11.

POWER – mW

IDD DYNAMIC

							220
																					1
							200																	205mW
							180
						mW	160
																								157mW
																		VDD = 5.5V
						–
						POWER	140
												129mW
							120											VDD = 5.0V
																								118mW
							100
											100mW
							80											VDD = 4.5V
													74mW
							60
							10.00				13.83						20.00			25.00						30.00
																	FREQUENCY – MHz
70					IDD IDLE																						IDD IDLE n MODES 3
																			65
					1,2																															64mW
60										64mW									60
						VDD = 5.5V
																															IDD IDLE
50		51mW																	55
										49mW								mW
40						VDD = 5.0V													50				51mW
																		–
		38mW
										35mW								POWER												IDLE 16
		28mW				VDD = 4.5V																														43mW
30																			45
20																			40				41mW													42mW
																						40mW
																													IDLE 128
10																			35
0																			30
10.00		13.83			20.00		25.00				30.00								10.00		13.83						20.00							25.00			30.00
					FREQUENCY – MHz																						FREQUENCY – MHz

VALID FOR ALL TEMPERATURE GRADES.

1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.

3MAXIMUM POWER DISSIPATION AT VDD = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.

Figure 11. ADSP-2101 Power (Typical) vs. Frequency

–18–

REV. B

ADSP-21xx

SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)

POWER DISSIPATION EXAMPLE

To determine total power dissipation in a specific application, the following equation should be applied for each output:

C × VDD2 × f

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2101 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows:

Assumptions:

•External data memory is accessed every cycle with 50% of the address pins switching.

•External data memory writes occur every other cycle with 50% of the data pins switching.

•Each address and data pin has a 10 pF total load at the pin.

•The application operates at VDD = 5.0 V and tCK = 50 ns.

Total Power Dissipation = PINT + (C × VDD2 × f )

CAPACITIVE LOADING

Figures 12 and 13 show capacitive loading characteristics for the ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2161/2163.

	8
	7			VDD = 4.5V
ns	6
–
0V).2	5
-
8V.(0	4
TIME	3
	2
RISE
	1
	0
	0	25	50	75	100	125	150	175
				CL – pF

	PINT = internal power dissipation (from Figure 11).	Figure 12. Typical Output Rise Time vs. Load Capacitance, CL
	(C × VDD2 × f ) is calculated for each output:
		(at Maximum Ambient Operating Temperature)

				# of	× C	× VDD2		× f
Output				Pins
Address,				8	× 10 pF	× 52	V	× 20 MHz = 40.0 mW
		DMS
Data, WR				9	× 10 pF	× 52	V	× 10 MHz = 22.5 mW
				1	× 10 pF	× 52	V	× 10 MHz =	2.5 mW
RD
CLKOUT				1	× 10 pF	× 52	V	× 20 MHz =	5.0 mW
									70.0 mW

Total power dissipation for this example = PINT + 70.0 mW.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

TAMB = TCASE – (PD × θCA)

TCASE = Case Temperature in °C PD = Power Dissipation in W

θCA = Thermal Resistance (Case-to-Ambient)

θJA = Thermal Resistance (Junction-to-Ambient)

θJC = Thermal Resistance (Junction-to-Case)

Package	θJA	θJC	θCA
PGA	18°C/W	9°C/W	9°C/W
PLCC	27°C/W	16°C/W	11°C/W
PQFP	60°C/W	18°C/W	42°C/W
TQFP	60°C/W	18°C/W	42°C/W

	5
ns–	4
HOLDOR	3			VDD = 4.5V
	2
DELAY	1
OUTPUT	0
	–1
VALID	–2
	–3	25	50	75	100	125	150
	0							175
				CL – pF

Figure 13. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)

REV. B

–19–

ADSP-21xx

SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)

TEST CONDITIONS

Figure 14 shows voltage reference levels for ac measurements.

3.0V

INPUT 1.5V

0.0V

2.0V

OUTPUT 1.5V

0.8V

The decay time, tDECAY, is dependent on the capacitative load, CL, and the current load, iL, on the output pin. It can be

approximated by the following equation:

tDECAY = CL ×i0.5 V

L

from which

tDIS = tMEASURED – tDECAY

is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving.

Figure 14. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The

output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in Figure 15. The time tMEASURED is the interval from when a reference signal reaches a high or low

voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage.

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in Figure 15. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

REFERENCE
SIGNAL
		tMEASURED
		tDIS		tENA
VOH (MEASURED)			VOH (MEASURED) – 0.5V	2.0V	VOH (MEASURED)
	OUTPUT
VOL (MEASURED)			VOL (MEASURED) +0.5V	1.0V	VOL (MEASURED)
	tDECAY
	OUTPUT STOPS			OUTPUT STARTS
				DRIVING
		DRIVING
				HIGH-IMPEDANCE STATE.
				TEST CONDITIONS CAUSE
				THIS VOLTAGE LEVEL TO BE
				APPROXIMATELY 1.5V.

Figure 15. Output Enable/Disable

IOL

TO

OUTPUT +1.5V

PIN

50pF

IOH

Figure 16. Equivalent Device Loading for AC Measurements (Except Output Enable/Disable)

–20–

REV. B