Analog Devices ADSP-2185NKST-320, ADSP-2185NKCA-320, ADSP-2189NKST-320, ADSP-2189NKCA-320, ADSP-2189NBST-320 Datasheet

a

DSP Microcomputer

ADSP-218xN Series

PERFORMANCE FEATURES

12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS Sustained Performance

Single-Cycle Instruction Execution Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION FEATURES

ADSP-2100 Family Code Compatible (Easy to Use Algebraic Syntax), with Instruction Set Extensions

Up to 256K Bytes of On-Chip RAM, Configured as Up to 48K Words Program Memory RAM

Up to 56K Words Data Memory RAM

Dual-Purpose Program Memory for Both Instruction and Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA

SYSTEM INTERFACE FEATURES

Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation All Inputs Tolerate up to 3.6 V Regardless of Mode

16-Bit Internal DMA Port for High-Speed Access to OnChip Memory (Mode Selectable)

4M-Byte Memory Interface for Storage of Data Tables and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)

Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System Signaling

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in Final Systems

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

CONTROL

MEMORY

DATA ADDRESS

PROGRAM

DATA

GENERATORS

PROGRAM

MEMORY

MEMORY

UP TO

UP TO

DAG1

DAG2

SEQUENCER

48K 24-BIT

56K 16-BIT

.

e

r

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h

m

a

r PROGRAM MEMORY ADDRESS

g

a

i

d

k

DATA MEMORY ADDRESS

c

o

l

b

p

i

PROGRAM MEMORY DATA

h

c

t

r

e

s

DATA MEMORY DATA

In

SERIAL PORTS

ARITHMETIC UNITS

ALU

MAC

SHIFTER

SPORT0

SPORT1

ADSP-2100 BASE

ARCHITECTURE

		FULL MEMORY MODE
	PROGRAMMABLE	EXTERNAL
	I/O
		ADDRESS
	AND
		BUS
	FLAGS
		EXTERNAL
		DATA
		BUS
		BYTE DMA
		CONTROLLER
		OR
		EXTERNAL
		DATA
		BUS

TIMER

INTERNAL

DMA

PORT

HOST MODE

ICE-Port is a trademark of Analog Devices, Inc.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:[phone]	http://www.analog.com
Fax:[phone]	© Analog Devices, Inc., 2001

ADSP-218xN Series

GENERAL DESCRIPTION

The ADSP-218xN series consists of six single chip microcomputers optimized for digital signal processing applications. The high-level block diagram for the ADSP-218xN series members appears on the previous page. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision. Specific family members are shown in Table 1.

Table 1. ADSP-218xN DSP Microcomputer Family

	Program
	Memory	Data Memory
Device	(K Words)	(K Words)
ADSP-2184N	4	4
ADSP-2185N	16	16
ADSP-2186N	8	8
ADSP-2187N	32	32
ADSP-2188N	48	56
ADSP-2189N	32	48

ADSP-218xN series members combine the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.

ADSP-218xN series members integrate up to 256K bytes of on-chip memory configured as up to 48K words (24-bit) of program RAM, and up to 56K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-218xN is available in a 100-lead LQFP package and 144-Ball Mini-BGA.

Fabricated in a high-speed, low-power, 0.18 µm CMOS process, ADSP-218xN series members operate with a 12.5 ns instruction cycle time. Every instruction can execute in a single processor cycle.

The ADSP-218xN’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, ADSP-218xN series members can:

•Generate the next program address

•Fetch the next instruction

•Perform one or two data moves

•Update one or two data address pointers

•Perform a computational operation

VisualDSP++ and EZ-KIT Lite are trademarks of Analog Devices, Inc.

This takes place while the processor continues to:

•Receive and transmit data through the two serial ports

•Receive and/or transmit data through the internal DMA port

•Receive and/or transmit data through the byte DMA port

•Decrement timer

DEVELOPMENT SYSTEM

Analog Devices’ wide range of software and hardware development tools supports the ADSP-218xN series. The DSP tools include an integrated development environment, an evaluation kit, and a serial port emulator.

VisualDSP++™ is an integrated development environment, allowing for fast and easy development, debug, and deployment. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder); a linker; a PROM-splitter utility; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that

includes DSP and mathematical functions.

Debugging both C and assembly programs with the VisualDSP++ debugger, programmers can:

•View mixed C and assembly code (interleaved source and object information)

•Insert break points

•Set conditional breakpoints on registers, memory, and stacks

•Trace instruction execution

•Fill and dump memory

•Source level debugging

The VisualDSP++ IDE lets programmers define and manage DSP software development. The dialog boxes and property pages let programmers configure and manage all of the ADSP-218xN development tools, including the syntax highlighting in the VisualDSP++ editor. This capability controls how the development tools process inputs and generate outputs.

The ADSP-2189M EZ-KIT Lite™ provides developers with a cost-effective method for initial evaluation of the powerful ADSP-218xN DSP family architecture. The ADSP-2189M EZ-KIT Lite includes a stand-alone ADSP2189M DSP board supported by an evaluation suite of VisualDSP++. With this EZ-KIT Lite, users can learn about DSP hardware and software development and evaluate potential applications of the ADSP-218xN series. The ADSP-2189M EZ-KIT Lite provides an evaluation suite of the VisualDSP++ development environment with the

C compiler, assembler, and linker. The size of the DSP erxecutable that can be built using the EZ-KIT Lite tools is limited to 8K words.

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ADSP-218xN Series

The EZ-KIT Lite includes the following features:

•75 MHz ADSP-2189M

•Full 16-Bit Stereo Audio I/O with AD73322 Codec

•RS-232 Interface

•EZ-ICE Connector for Emulator Control

•DSP Demonstration Programs

•Evaluation Suite of VisualDSP++

The ADSP-218x EZ-ICE® Emulator provides an easier and more cost-effective method for engineers to develop and optimize DSP systems, shortening product development cycles for faster time-to-market. ADSP-218xN series members integrate on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. ADSP-218xN series members need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.The EZ-ICE performs a full range of functions, including:

•In-target operation

•Up to 20 breakpoints

•Single-step or full-speed operation

•Registers and memory values can be examined and altered

•PC upload and download functions

•Instruction-level emulation of program booting and execution

•Complete assembly and disassembly of instructions

•C source-level debugging

Additional Information

This data sheet provides a general overview of ADSP218xN series functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference and the ADSP218x DSP Instruction Set Reference.

ARCHITECTURE OVERVIEW

The ADSP-218xN series instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-218xN assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

The functional block diagram is an overall block diagram of the ADSP-218xN series. The processor contains three independent computational units: the ALU, the multiplier/ accumulator (MAC), and the shifter. The computational

EZ-ICE is a registered trademark of Analog Devices, Inc.

units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs singlecycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations.

The shifter can be used to efficiently implement numeric format control, including multiword and block floatingpoint representations.

The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, ADSP-218xN series members execute looped code with zero overhead; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers.

Five internal buses provide efficient data transfer:

•Program Memory Address (PMA) Bus

•Program Memory Data (PMD) Bus

•Data Memory Address (DMA) Bus

•Data Memory Data (DMD) Bus

•Result (R) Bus

The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded offchip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses.

Program memory can store both instructions and data, permitting ADSP-218xN series members to fetch two operands in a single cycle, one from program memory and one from data memory. ADSP-218xN series members can fetch an operand from program memory and the next instruction in the same cycle.

In lieu of the address and data bus for external memory connection, ADSP-218xN series members may be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16

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ADSP-218xN Series

data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSP’s on-chip program and data RAM.

An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-218xN to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted.

ADSP-218xN series members can respond to eleven interrupts. There can be up to six external interrupts (one edgesensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORT), the Byte DMA port, and the power-down

circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation.

Each port can generate an internal programmable serial clock or accept an external serial clock.

ADSP-218xN series members provide up to 13 generalpurpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs.

A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).

Serial Ports

ADSP-218xN series members incorporate two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication.

Following is a brief list of the capabilities of the ADSP218xN SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference.

•SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.

•SPORTs can use an external serial clock or generate their own serial clock internally.

•SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings.

•SPORTs support serial data word lengths from 3 to

16 bits and provide optional A-law and -law companding, according to CCITT recommendation G.711.

•SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.

•SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer.

•SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream.

•SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration.

PIN DESCRIPTIONS

ADSP-218xN series members are available in a 100-lead LQFP package and a 144-Ball Mini-BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text in Table 2, while alternate functionality is shown in italics.

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ADSP-218xN Series

Table 2. Common-Mode Pins

Pin Name

# of Pins

I/O

Function

1

I

Processor Reset Input

RESET

BR

1

I

Bus Request Input

BG

1

O

Bus Grant Output

BGH

1

O

Bus Grant Hung Output

DMS

1

O

Data Memory Select Output

PMS

1

O

Program Memory Select Output

IOMS

1

O

Memory Select Output

BMS

1

O

Byte Memory Select Output

1

O

Combined Memory Select Output

CMS

1

O

Memory Read Enable Output

RD

WR

1

O

Memory Write Enable Output

1

I

Edgeor Level-Sensitive Interrupt Request1

IRQ2

PF7

I/O

Programmable I/O pin

1

I

Level-Sensitive Interrupt Requests1

IRQL1

PF6

I/O

Programmable I/O Pin

1

I

Level-Sensitive Interrupt Requests1

IRQL0

PF5

I/O

Programmable I/O Pin

1

I

Edge-Sensitive Interrupt Requests1

IRQE

PF4

I/O

Programmable I/O Pin

Mode D

1

I

Mode Select Input—Checked Only During

RESET

PF3

I/O

Programmable I/O Pin During Normal Operation

Mode C

1

I

Mode Select Input—Checked Only During

RESET

PF2

I/O

Programmable I/O Pin During Normal Operation

Mode B

1

I

Mode Select Input—Checked Only During

RESET

PF1

I/O

Programmable I/O Pin During Normal Operation

Mode A

1

I

Mode Select Input—Checked Only During

RESET

PF0

I/O

Programmable I/O Pin During Normal Operation

CLKIN

1

I

Clock Input

XTAL

1

O

Quartz Crystal Output

CLKOUT

1

O

Processor Clock Output

SPORT0

5

I/O

Serial Port I/O Pins

SPORT1

5

I/O

Serial Port I/O Pins

Edgeor Level-Sensitive Interrupts, FI, FO2

IRQ1–0, FI, FO

PWD

1

I

Power-Down Control Input

PWDACK

1

O

Power-Down Acknowledge Control Output

FL0, FL1, FL2

3

O

Output Flags

VDDINT

2

I

Internal VDD (1.8 V) Power (LQFP)

VDDEXT

4

I

External VDD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP)

GND

10

I

Ground (LQFP)

VDDINT

4

I

Internal VDD (1.8 V) Power (Mini-BGA)

VDDEXT

7

I

External VDD (1.8 V, 2.5 V, or 3.3 V) Power (Mini-

BGA)

GND

20

I

Ground (Mini-BGA)

EZ-Port

9

I/O

For Emulation Use

1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag.

2SPORT configuration determined by the DSP System Control Register. Software configurable.

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ADSP-218xN Series

Memory Interface Pins

signals at specific pins of the DSP during either of the two

ADSP-218xN series members can be used in one of two

operating modes (Full Memory or Host). A signal in one

modes: Full Memory Mode, which allows BDMA operation

table shares a pin with a signal from the other table, with the

with full external overlay memory and I/O capability, or

active signal determined by the mode that is set. For the

Host Mode, which allows IDMA operation with limited

shared pins and their alternate signals (e.g., A4/IAD3), refer

external addressing capabilities.

to the package pinouts in Table 27 on page 40 and Table 28

The operating mode is determined by the state of the Mode

on page 42.

C pin during

and cannot be changed while the

RESET

processor is running. Table 3 and Table 4 list the active

Table 3. Full Memory Mode Pins (Mode C = 0)

Pin Name

# of Pins

I/O

Function

A13–0

14

O

Address Output Pins for Program, Data, Byte, and I/O Spaces

D23–0

24

I/O

Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used

as Byte Memory Addresses.)

Table 4. Host Mode Pins (Mode C = 1)

Pin Name

# of Pins

I/O

Function

IAD15–0

16

I/O

IDMA Port Address/Data Bus

A0

1

O

Address Pin for External I/O, Program, Data, or Byte Access1

D23–8

16

I/O

Data I/O Pins for Program, Data, Byte, and I/O Spaces

1

I

IDMA Write Enable

IWR

IRD

1

I

IDMA Read Enable

IAL

1

I

IDMA Address Latch Pin

1

I

IDMA Select

IS

IACK

1

O

IDMA Port Acknowledge Configurable in Mode D; Open Drain

1In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.

Terminating Unused Pins

Table 5 shows the recommendations for terminating unused pins.

Table 5. Unused Pin Terminations

I/O

3-State

Reset

Pin Name1

(Z)2

State

Hi-Z3 Caused By

Unused Configuration

XTAL

O

O

Float

CLKOUT

O

O

Float4

A13–1 or

O (Z)

Hi-Z

BR,

EBR

Float

IAD12–0

I/O (Z)

Hi-Z

IS

Float

A0

O (Z)

Hi-Z

BR,

EBR

Float

D23–8

I/O (Z)

Hi-Z

BR,

EBR

Float

D7 or

I/O (Z)

Hi-Z

BR,

EBR

Float

IWR

I

I

High (Inactive)

D6 or

I/O (Z)

Hi-Z

BR,

EBR

Float

IRD

I

I

BR,

EBR

High (Inactive)

D5 or

I/O (Z)

Hi-Z

Float

IAL

I

I

Low (Inactive)

D4 or

I/O (Z)

Hi-Z

Float

BR,

EBR

IS

I

I

High (Inactive)

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ADSP-218xN Series

Table 5. Unused Pin Terminations (Continued)

I/O

3-State

Reset

Pin Name1

(Z)2

State

Hi-Z3 Caused By

Unused Configuration

D3 or

I/O (Z)

Hi-Z

Float

BR,

EBR

IACK

Float

D2–0 or

I/O (Z)

Hi-Z

Float

BR,

EBR

IAD15–13

I/O (Z)

Hi-Z

IS

Float

PMS

O (Z)

O

BR,

EBR

Float

DMS

O (Z)

O

BR,

EBR

Float

BMS

O (Z)

O

BR,

EBR

Float

IOMS

O (Z)

O

BR,

EBR

Float

CMS

O (Z)

O

BR,

EBR

Float

RD

O (Z)

O

BR,

EBR

Float

WR

O (Z)

O

BR,

EBR

Float

BR

I

I

High (Inactive)

BG

O (Z)

O

EE

Float

BGH

O

O

Float

IRQ2/

PF7

I/O (Z)

I

Input = High (Inactive) or Program as

Output, Set to 1, Let Float5

IRQL1/

PF6

I/O (Z)

I

Input = High (Inactive) or Program as

Output, Set to 1, Let Float5

IRQL0/

PF5

I/O (Z)

I

Input = High (Inactive) or Program as

Output, Set to 1, Let Float5

IRQE/

PF4

I/O (Z)

I

Input = High (Inactive) or Program as

Output, Set to 1, Let Float5

PWD

I

I

High

SCLK0

I/O

I

Input = High or Low, Output = Float

RFS0

I/O

I

High or Low

DR0

I

I

High or Low

TFS0

I/O

I

High or Low

DT0

O

O

Float

SCLK1

I/O

I

Input = High or Low, Output = Float

I/O

I

High or Low

RFS1/IRQ0

DR1/FI

I

I

High or Low

I/O

I

High or Low

TFS1/IRQ1

DT1/FO

O

O

Float

EE

I

I

Float

I

I

Float

EBR

EBG

O

O

Float

ERESET

I

I

Float

EMS

O

O

Float

EINT

I

I

Float

ECLK

I

I

Float

ELIN

I

I

Float

ELOUT

O

O

Float

1CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used.

2All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive. 3Hi-Z = High Impedance.

4If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.

5If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float.

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ADSP-218xN Series

Interrupts

The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. ADSP-218xN series members provide four dedicated external interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7–4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI and FO, for a total of six external interrupts. The ADSP-218xN also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either levelor edge-sensitive. IRQL0 and IRQL1 are

level-sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table 6.

Table 6. Interrupt Priority and Interrupt Vector

Addresses

							Interrupt Vector Address
	Source Of Interrupt						(Hex)
	Reset (or Power-Up with						0x0000	(Highest Priority)
	PUCR = 1)
	Power-Down						0x002C
	(Nonmaskable)
							0x0004
	IRQ2
	IRQL1						0x0008
	IRQL0						0x000C
	SPORT0 Transmit						0x0010
	SPORT0 Receive						0x0014
	IRQE						0x0018
	BDMA Interrupt						0x001C
	SPORT1 Transmit or						0x0020
	IRQ1
	SPORT1 Receive or				IRQ0		0x0024
	Timer						0x0028	(Lowest Priority)

Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable.

ADSP-218xN series members mask all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edgeor level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts.

The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are 12 levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK:

ENA INTS;

DIS INTS;

Disabling the interrupts does not affect serial port autobuffering or DMA. When the processor is reset, interrupt servicing is enabled.

LOW-POWER OPERATION

ADSP-218xN series members have three low-power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are:

•Power-Down

•Idle

•Slow Idle

The CLKOUT pin may also be disabled to reduce external power dissipation.

Power-Down

ADSP-218xN series members have a low-power feature that lets the processor enter a very low-power dormant state through hardware or software control. Following is a brief list of power-down features. Refer to the ADSP-218x DSP Hardware Reference, “System Interface” chapter, for detailed information about the power-down feature.

•Quick recovery from power-down. The processor begins executing instructions in as few as 200 CLKIN cycles.

•Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 200 CLKIN cycle recovery.

•Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle start-up.

•Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The powerdown interrupt also can be used as a nonmaskable, edgesensitive interrupt.

•Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state.

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ADSP-218xN Series

•The RESET pin also can be used to terminate powerdown.

•Power-down acknowledge pin (PWDACK) indicates when the processor has entered power-down.

Idle

When the ADSP-218xN is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA, and autobuffer cycle steals still occur.

Slow Idle

The IDLE instruction is enhanced on ADSP-218xN series members to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction.

The format of the instruction is:

IDLE (N);

where N = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, ADSP-218xN series members remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles).

SYSTEM INTERFACE

Figure 1 shows typical basic system configurations with the ADSP-218xN series, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (mode-selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. ADSP-218xN series members also provide four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals.

FULL MEMORY MODE

HOST MEMORY MODE

1/2X CLOCK

ADSP-218xN

ADSP-218xN

CLKIN

1/2X CLOCK

CLKIN

OR

XTAL

ADDR13–0 14

A13–0

OR

XTAL

CRYSTAL

CRYSTAL

1

FL0–2

D23–16

A0–A21

BYTE

FL0–2

A0

IRQ2/PF7

16

IRQ2/PF7

24

D15–8

MEMORY

IRQE/PF4

DATA23–0

DATA

IRQE/PF4

DATA23–8

IRQL0/PF5

IRQL0/PF5

CS

IRQL1/PF6

BMS

IRQL1/PF6

BMS

SERIAL DEVICE

SERIAL DEVICE

MODE D/PF3

WR

A10–0

ADDR

e

RD

r

MODE C/PF2

D23–8

I/O SPACEe

h

MODE A/PF0

(PERIPHERALS)

DATA

m

a

MODE B/PF1

r

2048g LOCATIONS

a

IOMS

i

CS d

SPORT1

e

c

a

A13–0

f

r

SCLK1

e

t

OVERLAY

n

ADDR

RFS1 OR IRQ0

i

D23–0m

MEMORY

TFS1 OR IRQ1

e

t

s

DATA

DT1 OR FO

y

TWO 8K

s

PMS

t

DR1 OR FI

r

PM SEGMENTS

e

DMSI

s

n

TWO 8K

SPORT0

CMS

DM SEGMENTS

	SCLK0	BR
	RFS0
		BG
	TFS0
		BGH
	DT0
		PWD
	DR0
		PWDACK

								MODE D/PF3		WR
								MODE C/PF2
										RD
								MODE A/PF0
								MODE B/PF1
								SPORT1		IOMS
								SCLK1
SERIAL								RFS1 OR IRQ0
								TFS1 OR IRQ1
DEVICE
								DT1 OR FO
								DR1 OR FI		PMS
								SPORT0		DMS
								SCLK0		CMS
								RFS0
SERIAL										BR
								TFS0
DEVICE
								DT0		BG
								DR0		BGH
										PWD
								IDMA PORT
									PWDACK
								IRD/D6
SYSTEM								IWR/D7
INTERFACE								IS/D4
OR								IAL/D5
µCONTROLLER								IACK/D3
								IAD15-0
				16

Figure 1. Basic System Interface

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ADSP-218xN Series

Clock Signals

ADSP-218xN series members can be clocked by either a crystal or a TTL-compatible clock signal.

The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during normal operation. The only exception is while the processor is in the power-down state. For additional information, refer to the ADSP-218x DSP Hardware Reference, for detailed information on this power-down feature.

If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL pin must be left unconnected.

ADSP-218xN series members use an input clock with a frequency equal to half the instruction rate; a 40 MHz input clock yields a 12.5 ns processor cycle (which is equivalent to 80 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled.

Because ADSP-218xN series members include an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 2. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallelresonant, fundamental frequency, microprocessor-grade crystal should be used.

A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.

		CLKIN				XTAL		CLKOUT

DSP

Figure 2. External Crystal Connections

RESET

The RESET signal initiates a master reset of the ADSP218xN. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse-width specification (tRSP).

The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an external Schmitt trigger is recommended.

The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the bootloading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.

POWER SUPPLIES

ADSP-218xN series members have separate power supply

connections for the internal (VDDINT) and external (VDDEXT) power supplies. The internal supply must meet the 1.8 V

requirement. The external supply can be connected to a 1.8 V, 2.5 V, or 3.3 V supply. All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6 V, regardless of the external supply voltage. This feature provides maximum flexibility in mixing 1.8 V, 2.5 V, or 3.3 V components.

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ADSP-218xN Series

MODES OF OPERATION

The ADSP-218xN series modes of operation appear in

Table 7.

Table 7. Modes of Operation

Mode D	Mode C	Mode B	Mode A		Booting Method
X	0	0	0		BDMA feature is used to load the first 32 program memory words
					from the byte memory space. Program execution is held off until all
					32 words have been loaded. Chip is configured in Full Memory
					Mode.1
X	0	1	0		No automatic boot operations occur. Program execution starts at
					external memory location 0. Chip is configured in Full Memory
					Mode. BDMA can still be used, but the processor does not automat-
					ically use or wait for these operations.
0	1	0	0		BDMA feature is used to load the first 32 program memory words
					from the byte memory space. Program execution is held off until all
					32 words have been loaded. Chip is configured in Host Mode.		IACK
					has active pull-down. (Requires additonal hardware.)
0	1	0	1		IDMA feature is used to load any internal memory as desired.
					Program execution is held off until the host writes to internal
					program memory location 0. Chip is configured in Host Mode.
						has active pull-down.1
					IACK
1	1	0	0		BDMA feature is used to load the first 32 program memory words
					from the byte memory space. Program execution is held off until all
					32 words have been loaded. Chip is configured in Host Mode;
							IACK
					requires external pull-down. (Requires additonal hardware.)
1	1	0	1		IDMA feature is used to load any internal memory as desired.
					Program execution is held off until the host writes to internal
					program memory location 0. Chip is configured in Host Mode.
						requires external pull-down.1
					IACK

1Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

Setting Memory Mode

Memory Mode selection for the ADSP-218xN series is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive.

Passive Configuration

Passive Configuration involves the use of a pull-up or pulldown resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as

an output in the DSP application, a weak pull-up or pulldown resistance, on the order of 10 k , can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor’s output driver. For minimum power consumption during powerdown, reconfigure PF2 to be an input, as the pull-up or pulldown resistance will hold the pin in a known state, and will not switch.

Active Configuration

Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output enable should be connected to the DSP’s RESET

signal such that it only drives the PF2 pin when RESET is

active (low). When RESET is deasserted, the driver should be three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three-stated buffer. This ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver’s level hover around the logic switching point.

IDMA ACK Configuration

Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be “wire ORed.” Mode D = 1 and in host

mode: IACK is an open drain and requires an external

pull-down, but multiple IACK pins can be “wire ORed” together.

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ADSP-218xN Series

MEMORY ARCHITECTURE

The ADSP-218xN series provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O.

Refer to Figure 3 through Figure 8, Table 8 on page 14, and Table 9 on page 14 for PM and DM memory allocations in the ADSP-218xN series.

	PROGRAM MEMORY			PROGRAM MEMORY			DATA MEMORY
	MODEB = 1			MODEB = 0
0X3FFF		0X3FFF			0X3FFF		32 MEMORY-MAPPED
				PM OVERLAY 1,2	0X3FE0		CONTROL REGISTERS
				(EXTERNAL PM)
	RESERVED				0X3FDF		4064 RESERVED
				PM OVERLAY 0
				(RESERVED)	0X3000		WORDS
0X2000		0X2000			0X2FFF		INTERNAL DM
0X1FFF		0X1FFF			0X2000
	EXTERNAL PM			RESERVED	0X1FFF		DM OVERLAY 1,2
		0X1000					(EXTERNAL DM)
		0X0FFF		INTERNAL PM			DM OVERLAY 0
							(RESERVED)
		0X0000
0X0000					0X0000

Figure 3. ADSP-2184 Memory Architecture

	PROGRAM MEMORY			PROGRAM MEMORY			DATA MEMORY
	MODEB = 1			MODEB = 0
0X3FFF		0X3FFF			0X3FFF		32 MEMORY-MAPPED
				PM OVERLAY 1,2	0X3FE0		CONTROL REGISTERS
				(EXTERNAL PM)
	RESERVED				0X3FDF
				PM OVERLAY 0
							INTERNAL DM
				(RESERVED)
0X2000		0X2000			0X2000
0X1FFF		0X1FFF			0X1FFF
							DM OVERLAY 1,2
	EXTERNAL PM			INTERNAL PM			(EXTERNAL DM)
							DM OVERLAY 0
							(INTERNAL DM)
0X0000		0X0000			0X0000

Figure 4. ADSP-2185 Memory Architecture

	PROGRAM MEMORY			PROGRAM MEMORY			DATA MEMORY
	MODEB = 1			MODEB = 0
0X3FFF		0X3FFF			0X3FFF		32 MEMORY-MAPPED
				PM OVERLAY 1,2	0X3FE0		CONTROL REGISTERS
				(EXTERNAL PM)
	RESERVED				0X3FDF
				PM OVERLAY 0
				(RESERVED)			INTERNAL DM
0X2000		0X2000
0X1FFF		0X1FFF			0X2000
	EXTERNAL PM			INTERNAL PM	0X1FFF		DM OVERLAY 1,2
							(EXTERNAL DM)
							DM OVERLAY 0
							(RESERVED)
0X0000		0X0000			0X0000

Figure 5. ADSP-2186 Memory Architecture

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							ADSP-218xN Series
	PROGRAM MEMORY			PROGRAM MEMORY			DATA MEMORY
	MODEB = 1			MODEB = 0
0X3FFF		0X3FFF			0X3FFF		32 MEMORY-MAPPED
				PM OVERLAY 1,2			CONTROL REGISTERS
					0X3FE0
				(EXTERNAL PM)
	RESERVED				0X3FDF
				PM OVERLAY 0,4,5
				(INTERNAL PM)			INTERNAL DM
0X2000		0X2000
0X1FFF		0X1FFF			0X2000
	EXTERNAL PM			INTERNAL PM	0X1FFF		DM OVERLAY 1,2
							(EXTERNAL DM)
							DM OVERLAY 0,4,5
							(INTERNAL DM)
0X0000		0X0000			0X0000

Figure 6. ADSP-2187 Memory Architecture

	PROGRAM MEMORY			PROGRAM MEMORY			DATA MEMORY
	MODEB = 1			MODEB = 0
0x3FFF		0x3FFF			0x3FFF		32 MEMORY-MAPPED
				PM OVERLAY 1,2
							CONTROL REGISTERS
				(EXTERNAL PM)	0x3FE0
	RESERVED			PM OVERLAY	0x3FDF
				0,4,5,6,7			INTERNAL DM
				(INTERNAL PM)
0x2000		0x2000			0x2000
0x1FFF		0x1FFF
					0x1FFF		DM OVERLAY 1,2
	EXTERNAL PM			INTERNAL PM			(EXTERNAL DM)
							DM OVERLAY
							0,4,5,6,7,8
0x0000		0x0000			0x0000		(INTERNAL DM)

Figure 7. ADSP-2188 Memory Architecture

	PROGRAM MEMORY			PROGRAM MEMORY			DATA MEMORY
	MODEB = 1			MODEB = 0
0X3FFF		0X3FFF			0X3FFF		32 MEMORY-MAPPED
				PM OVERLAY 1,2
							CONTROL REGISTERS
				(EXTERNAL PM)	0X3FE0
	RESERVED				0X3FDF
				PM OVERLAY 0,4,5
				(INTERNAL PM)			INTERNAL DM
0X2000		0X2000			0X2000
0X1FFF		0X1FFF
					0X1FFF		DM OVERLAY 1,2
	EXTERNAL PM			INTERNAL PM			(EXTERNAL DM)
							DM OVERLAY
							0,4,5,6,7
0X0000		0X0000			0X0000		(INTERNAL DM)

Figure 8. ADSP-2189 Memory Architecture

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ADSP-218xN Series

Program Memory

Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-218xN series has up to 48K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces, using the external data bus.

Table 8. PMOVLAY Bits

Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted data bus that is only 16 bits wide.

Processor	PMOVLAY	Memory	A13	A12–0
ADSP-2184N	No Internal	Not Applicable	Not Applicable	Not Applicable
	Overlay Region
ADSP-2185N	0	Internal Overlay	Not Applicable	Not Applicable
ADSP-2186N	No Internal	Not Applicable	Not Applicable	Not Applicable
	Overlay Region
ADSP-2187N	0, 4, 5	Internal Overlay	Not Applicable	Not Applicable
ADSP-2188N	0, 4, 5, 6, 7	Internal Overlay	Not Applicable	Not Applicable
ADSP-2189N	0, 4, 5	Internal Overlay	Not Applicable	Not Applicable
All Processors	1	External Overlay 1	0	13 LSBs of Address Between 0x2000 and
				0x3FFF
All Processors	2	External Overlay 2	1	13 LSBs of Address Between 0x2000 and
				0x3FFF

Data Memory

Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memorymapped control registers. The ADSP-218xN series has up to 56K words of Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses com-

Table 9. DMOVLAY Bits

plete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register and the wait state mode bit.

Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0).

Processor	DMOVLAY	Memory	A13	A12–0
ADSP-2184N	No Internal Overlay	Not Applicable	Not Applicable	Not Applicable
	Region
ADSP-2185N	0	Internal Overlay	Not Applicable	Not Applicable
ADSP-2186N	No Internal Overlay	Not Applicable	Not Applicable	Not Applicable
	Region
ADSP-2187N	0, 4, 5	Internal Overlay	Not Applicable	Not Applicable
ADSP-2188N	0, 4, 5, 6, 7, 8	Internal Overlay	Not Applicable	Not Applicable
ADSP-2189N	0, 4, 5, 6, 7	Internal Overlay	Not Applicable	Not Applicable
All Processors	1	External Overlay 1	0	13 LSBs of Address
				Between 0x0000
				and 0x1FFF
All Processors	2	External Overlay 2	1	13 LSBs of Address
				Between 0x0000
				and 0x1FFF

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ADSP-218xN Series

Memory-Mapped Registers (New to the ADSP-218xM and N series)

ADSP-218xN series members have three memory-mapped registers that differ from other ADSP-21xx Family DSPs. The slight modifications to these registers (Wait State Control, Programmable Flag and Composite Select Control, and System Control) provide the ADSP-218xN’s wait state

and BMS control features. Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a grey field. These bits should always be written with zeros.

I/O Space (Full Memory Mode)

ADSP-218xN series members support an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined.

Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0–3 as shown in Figure 9, which in combination with the wait state mode bit, specify up to 15 wait states to be automatically generated for each of four regions. The wait states act on address ranges, as shown in Table 10.

Note: In Full Memory Mode, all 2048 locations of I/O space are directly addressable. In Host Memory Mode, only address pin A0 is available; therefore, additional logic is required externally to achieve complete addressability of the 2048 I/O space locations.

Table 10. Wait States

Address Range	Wait State Register
0x000–0x1FF	IOWAIT0 and Wait State Mode
	Select Bit
0x200–0x3FF	IOWAIT1 and Wait State Mode
	Select Bit
0x400–0x5FF	IOWAIT2 and Wait State Mode
	Select Bit
0x600–0x7FF	IOWAIT3 and Wait State Mode
	Select Bit

WAIT STATE CONTROL

15		14		13	12			11		10				9		8			7					6		5		4					3		2				r		0
																																						e1
																																						t
																																					s
																																				i
1		1		1		1		1		1				1			1			1				1		1			1				1e			g			1		1 DM(0X3FFE)
																																				1
																																	R
																															l
																														o
																													r
																												t
			DWAIT					IOWAIT3									IOWAIT2										n										IOWAIT0
																										oIOWAIT1
																								C
																						e
																						t
																					a
																					t
WAIT STATE MODE SELECT																			S
																	it
																a
0 = NORMAL MODE (PWAIT,WDWAIT, IOWAIT0–3 = N WAIT STATES,
											t
											r
											e
RANGING FROM 0 TOs 7)
									n
								I

1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING FROM 0 TO 15)

Figure 9. Wait State Control Register

Composite Memory Select

ADSP-218xN series members have a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit.

The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit.

See Figure 10 and Figure 11 for illustration of the programmable flag and composite control register and the system control register.

PROGRAMMABLE FLAG AND COMPOSITE

SELECT CONTROL

15		14		13		12		11		10		9			8		7	6		5		4	3		2	1	0
1		1		1		1		1		0			1		1		0	0		0		0	0		0	0	0		DM(0X3FE6)
	B M W A I T									C M S S E L											P F T Y P E
										0		= D IS A B L E CMS									0	= IN P U T
										1		= E N A B L E CMS									1	= O U T P U T

( W H E R E B IT : 1 1 - I O M , 1 0 - B M , 9 - D M , 8 - PM )

Figure 10. Programmable Flag and Composite Control

Register

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