Analog Devices AN605 Application Notes

a	AN-605
	APPLICATION NOTE

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Synchronizing Multiple AD9852 DDS-Based Synthesizers

by David Brandon

INTRODUCTION

Many applications require the generation of two or more sinusoidal or square wave signals with a known phase relationship between them. The AD9852 DDS IC from Analog Devices is capable of providing such signals. This application note offers detailed instructions on how to synchronize two or more of these devices and considers possible sources of phase error. For a quadrature application, see the AD9854 DDS with its built-in quadrature configuration; however, this application note would also apply to the AD9854 as well.

For successful synchronization, the user must have control over the timing relationship between REFCLK and the rising edge of the EXT I/O UPDATE CLK. The goal is to have all DDSs operating on the same SYSTEM CLK count and not off by ±1 or more counts from each DDS. Therefore, the EXT I/O UPDATE CLK must be made synchronous with the REFCLK.

For phase errors due to DAC output filtering mismatches, the AD9852 features programmable phase adjust that can null out these types of mismatches.

REF CLOCK

The first requirement for successful synchronization of multiple AD9852s is that there must be minimal phase error between the REFCLK inputs to all DDSs. Any difference in-phase between the REFCLK edges will result in a proportional phase difference at the DDS outputs. Therefore, the user must employ a careful clock distribution practice in the layout of the PCB (see Figure 1).

The AD9852 REFCLK input circuitry has an option of using differential inputs or a single-ended configuration. Differential REFCLK mode is recommended for its optimum switching characteristics. The REFCLK edges should have minimum input jitter and fast rise/fall times (less than 1 ns is recommended). A slow rise time on REFCLK can increase the phase error time because the voltage trip point of the input circuit varies from device to device.

	OPTIMUM LAYOUT
	A = B = C
			DDS NO.1
		A
		B
REFCLK				DDS NO. 2

C

DDS NO. 3

DDS NO. 1

DDS NO. 2

REFCLK DDS NO. 3

Figure 1. REFCLK Distribution

I/O UPDATE CLOCK

The I/O UPDATE CLK is responsible for transferring the contents of the I/O port buffer to the programming registers where the data becomes active. This clock has two modes of operation in which the DDS can supply the I/O UPDATE CLK, or the user can supply it. For synchronization reasons, external mode is highly recommended. Internal mode was not given consideration for complexity reasons.

AD9852 I/O INTERFACE DETAILS

Once a fast-edged and properly routed REFCLK signal is provided, the next timing requirement is the coincident transfer of the data into the DDS programming registers. The I/O UPDATE CLK transfers the contents of the I/O port buffer to the programming registers where data becomes active. Synchronization of multiple DDSs requires that the EXT I/O UPDATE CLK’s rising edge occur simultaneously at all DDSs, just like the REFCLK. In addition, the rising edge of the EXT I/O UPDATE CLK must occur at the proper time with respect to REFCLK.

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The AD9852 can be programmed in serial or parallel mode. Figure 2 depicts the parallel mode. If shown, the serial mode would display an additional 7-bit shift register and other support circuitry in front of the parallel data path. However, the main reason for showing this diagram is to view the paths of REFCLK and EXT I/O UPDATE CLK.

A few things to note in Figure 2 are how the SYSTEM CLK is derived and the inversion of REFCLK in singleended REFCLK mode. Also note, an asynchronous EXT

I/O UPDATE CLK will be made synchronous to the SYSTEM CLK via the edge detection circuitry (see Figure 3). However, it is incumbent upon the user to make it synchronous with the REFCLK to avoid a SYSTEM CLK count mismatch between DDSs.

Depending on the setting of the REFCLK mode (singleended or differential) and/or the use of the on-chip REFCLK multiplier (PLL), the timing relationship between REFCLK and EXT I/O UPDATE CLK will change. These timing changes will be addressed later.

			I/O PORT BUFFERS			PROGRAMMING
						REGISTERS
					ADDRESS
					6
			RD
			8		READBACK		320
		8
					MUX
DATA			8				8
	D		1 OF 40			0	8	1 OF 40
6	E	40	D	L	8		M
							U	D	Q
ADDRESS	C			A
	O			T		1 X
	D			C				F/F
	E			H				CK
			EN

UPDATE REGS

DDS

WR

1 OF 40

(SEE TIMING FOR

EDGE DETECT BELOW)

EXT

EDGE

I/O UPDATE

DETECT

CLOCK

REFCLKB

REFCLK

DIFFERENTIAL

MULTIPLIER

REFCLK

MODE

1 M

0 M

U

U

1 X

DIFF/SINGLE

0 X

SYSTEM CLOCK

Figure 2. AD9852 Parallel Interface Block Diagram

I/O PORT BUFFERS CONTENTS

ARE REGISTERED INTO

PROGRAMMING REGISTERS

FIRST SYSTEM TO SEE

FORMS RISING EDGE

FORMS FALLING EDGE

EXT I/O UPDATE CLK

OF UPDATE REGS

OF UPDATE REGS

SYSTEM CLK

0

1

2

3

EXT I/O UPDATE CLK

UPDATE REGS

Figure 3. Ext I/O Update CLK's Edge Detect Timing

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From the timing in Figure 3, it is essential that a proper time relationship exist between EXT I/O UPDATE CLK and the SYSTEM CLOCK for synchronization to occur. If this time relationship is met, then all SYSTEM CLOCKs are on the same count across all DDSs and not off by ±1 or more SYSTEM CLOCK counts. The user would control this relationship with the control of the rising edge of the EXT I/O UPDATE CLK with respect to the REFCLK. This timing relationship will be addressed in the SYNCHRONIZATION INSTRUCTIONS section.

RESET—BACKGROUND

A RESET must be given after power-up and prior to transferring any data to the DDS. This places the DDS output into a known phase, which becomes the common reference point that allows the synchronization of multiple DDSs.

RESET forces the AD9852’s phase accumulator state to become COS(0). When new data is sent simultaneously to multiple DDSs, a coherent phase relationship can be maintained, or the relative phase offset between multiple DDSs can be predictability shifted by means of the phase offset adjustment register. The AD9852 has 14 bits of phase-offset adjustment that amounts to a phase resolution of 0.022°. The phase-offset feature is located between the phase accumulator and the phase- to-amplitude converter.

SYNCHRONIZATION INSTRUCTIONS

Figure 4 presents one possible reference design for the successful synchronization of multiple DDSs. This example shows how to place two DDSs into the same phase relationship.

In Figure 4, the D flip-flop enables the EXT I/O UPDATE CLK to be synchronous with the REFCLK and provides a setup time. Proper operation may require additional time delay in the REFCLK path. This delay depends on the CK–to–Q propagation time of the flipflop. The recommended timing relationship between the EXT I/O UPDATE CLK (Pin 20) and the REFCLK (Pin 69) is depicted in Figures 5 and 6, depending on single-ended or differential REFCLK mode. Timing for the REFCLK multiplier enabled is depicted in Figures 8 and 9.

Here are some general instructions and recommendations for placing two DDSs into the same phase relationship (refer to Figure 4).

Note that there are two sets of instructions, with and without the REFCLK multiplier enabled.

Instructions (without the AD9852’s REFCLK multiplier enabled) to synchronize two DDSs.

1.Power up all devices and apply the common REFCLK.

2.Send a common RESET with a minimum high time of 10 REFCLK periods.

3.Program all DDSs for EXT I/O UPDATE CLK mode (bypass digital multipliers and inverse sync, if desired).

4.Program DDS No. 1 to the desired frequency and a phase offset of 0° without issuing an EXT I/O

UPDATE CLK.

5.Program DDS No. 2 to the exact same frequency and a phase offset of 0° without issuing an EXT I/O

UPDATE CLK.

THREE STATE

EXT I/0 UPDATE CLK

RESET

MICROPROCESSOR

OR FPGA

WRB NO.1

WRB NO.2

	DELAY
		REFCLK
CK		AD9852 NO. 1
D FLOP
EN		DATA/ADDRESS
D	Q
		WRB	ZERO
		EXT I/O UPDATE CLK	PHASE
			DIFFERENCE
		RESET
DATA/ADDRESS BUS		RESET
		EXT I/O UPDATE CLK
		WRB
		AD9852 NO. 2
		DATA/ADDRESS
		REFCLK

Figure 4. Application Circuit

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