Analog Devices ADSP-2181BST-115, ADSP-2181BS-133, ADSP-2181BS-115, ADSP-2181KST-160, ADSP-2181KST-133 Datasheet

a

DSP Microcomputer

ADSP-2181

FEATURES PERFORMANCE

25 ns Instruction Cycle Time from 20 MHz Crystal @ 5.0 Volts

40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power-Down Condition

Low Power Dissipation in Idle Mode INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction Set Extensions

80K Bytes of On-Chip RAM, Configured as

16K Words On-Chip Program Memory RAM

16K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction and Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units

Two Independent Data Address Generators Powerful Program Sequencer Provides

Zero Overhead Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler 128-Lead TQFP/128-Lead PQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to On-Chip Memory

4 MByte Memory Interface for Storage of Data Tables and Program Overlays

8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers

I/O Memory Interface with 2048 Locations Supports Parallel Peripherals

Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System Signaling

ICE-Port™ Emulator Interface Supports Debugging in Final Systems

ICE-Port is a trademark of Analog Devices, Inc.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN		PROGRAMMABLE
CONTROL		I/O

	DATA ADDRESS		MEMORY		FLAGS
		PROGRAM
	GENERATORS		PROGRAM	DATA	BYTE DMA
		SEQUENCER
	DAG 1 DAG 2		MEMORY	MEMORY
					CONTROLLER
					EXTERNAL
					ADDRESS
		PROGRAM MEMORY ADDRESS			BUS
		DATA MEMORY ADDRESS			EXTERNAL
		PROGRAM MEMORY DATA			DATA BUS
		DATA MEMORY DATA

DMA BUS

ARITHMETIC UNITS						SERIAL PORTS				TIMER	INTERNAL
											DMA
ALU		MAC		SHIFTER		SPORT 0		SPORT 1			PORT

ADSP-2100 BASE

ARCHITECTURE

GENERAL DESCRIPTION

The ADSP-2181 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2181 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.

The ADSP-2181 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2181 is available in 128-lead TQFP and 128lead PQFP packages.

In addition, the ADSP-2181 supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2181 operates with a 25 ns instruction cycle time. Every instruction can execute in a single processor cycle.

The ADSP-2181’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2181 can:

•Generate the next program address

•Fetch the next instruction

•Perform one or two data moves

•Update one or two data address pointers

•Perform a computational operation

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ADSP-2181

This takes place while the processor continues to:

•Receive and transmit data through the two serial ports

•Receive and/or transmit data through the internal DMA port

•Receive and/or transmit data through the byte DMA port

•Decrement timer

Development System

The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2181. The System Builder provides a high level method for defining the architecture of systems under

development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation’s GNU C Compiler, generates ADSP-2181 assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the entire ADSP-21xx family: an ADSP-2181 evaluation board with PC monitor software plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low-cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features:

•33 MHz ADSP-2181

•Full 16-bit Stereo Audio I/O with AD1847 SoundPort® Codec

•RS-232 Interface to PC with Windows 3.1 Control Software

•Stand-Alone Operation with Socketed EPROM

•EZ-ICE® Connector for Emulator Control

•DSP Demo Programs

The ADSP-218x EZ-ICE Emulator aids in the hardware debugging of ADSP-218x systems. The emulator consists of hardware, host computer resident software and the target board connector. The ADSP-218x integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection requiring fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-218x device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.

The EZ-ICE performs a full range of functions, including:

•In-target operation

•Up to 20 breakpoints

•Single-step or full-speed operation

•Registers and memory values can be examined and altered

•PC upload and download functions

•Instruction-level emulation of program booting and execution

•Complete assembly and disassembly of instructions

•C source-level debugging

See the Designing An EZ-ICE-Compatible Target System section of this data sheet for exact specifications of the EZ-ICE target board connector.

EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

Additional Information

This data sheet provides a general overview of ADSP-2181 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User’s Manual, Third Edition. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2181 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2181 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

Figure 1 is an overall block diagram of the ADSP-2181. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floatingpoint representations.

The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2181 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers.

Efficient data transfer is achieved with the use of five internal buses:

•Program Memory Address (PMA) Bus

•Program Memory Data (PMD) Bus

•Data Memory Address (DMA) Bus

•Data Memory Data (DMD) Bus

•Result (R) Bus

The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses.

Program memory can store both instructions and data, permitting the ADSP-2181 to fetch two operands in a single cycle, one from program memory and one from data memory. The

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ADSP-2181

ADSP-2181 can fetch an operand from program memory and the next instruction in the same cycle.

In addition to the address and data bus for external memory connection, the ADSP-2181 has a 16-bit Internal DMA port (IDMA port) for connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins.

The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH and BG). One execution mode (Go Mode) allows the ADSP-2181 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted.

The ADSP-2181 can respond to 13 possible interrupts, eleven of which are accessible at any given time. There can be up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port and the power-down circuitry. There is also a master RESET signal.

The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock.

The ADSP-2181 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, there are eight flags that are programmable as inputs or outputs and three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n processor cycles, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2181 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2181 SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third Edition for further details.

•SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.

•SPORTs can use an external serial clock or generate their own serial clock internally.

•SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of two pulsewidths and timings.

21xx CORE

ADSP-2181 INTEGRATION

								POWER-		2
								DOWN
								CONTROL
								LOGIC
			INSTRUCTION	PROGRAM	DATA
			REGISTER	SRAM	SRAM		BYTE	PROGRAMMABLE		8
				16K 3 24	16K 3	16
							DMA	I/O
DATA		DATA					CONTROLLER			3
ADDRESS		ADDRESS	PROGRAM
								FLAGS
GENERATOR		GENERATOR
			SEQUENCER
#1		#2
		PMA BUS	14					PMA BUS
									14
		DMA BUS	14					DMA BUS	MUX
									EXTERNAL
									ADDRESS
										BUS
		PMD BUS	24					PMD BUS	EXTERNAL
									DATA
			BUS							BUS
								DMD	MUX
			EXCHANGE
		DMD BUS						BUS		24
			16
INPUTINPUTREGS		INPUTINPUTREGSRE	INPUT REGS	COMPANDING					INTERNAL	16
					CIRCUITRY
									DMA
ALU		MAC	SHIFTER
									PORT
		MAC					TIMER
				TRANSMIT REG
OUTPUT REGS		OUTPUT REGS	OUTPUT REGS				TRANSMIT REG
OUTPUT	S	OUTPUT R		RECEIVE REG			RECEIVE REG
		16		SERIAL			SERIAL			4
				PORT 0			PORT 0	INTERRUPTS

R BUS

5

5

Figure 1. ADSP-2181 Block Diagram

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ADSP-2181

•SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and μ-law companding according to CCITT recommendation G.711.

•SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.

•SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer.

•SPORT0 has a multichannel interface to selectively receive and transmit a 24or 32-word, time-division multiplexed, serial bitstream.

•SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration.

Pin Descriptions

The ADSP-2181 is available in 128-lead TQFP and 128-lead PQFP packages.

PIN FUNCTION DESCRIPTIONS

	#
Pin	of	Input/
Name(s)	Pins	Output	Function
Address	14	O	Address Output Pins for Program,
			Data, Byte, and I/O Spaces
Data	24	I/O	Data I/O Pins for Program and
			Data Memory Spaces (8 MSBs
			Are Also Used as Byte Space
			Addresses)
RESET	1	I	Processor Reset Input
IRQ2	1	I	Edgeor Level-Sensitive
			Interrupt Request
IRQL0,
IRQL1	2	I	Level-Sensitive Interrupt
			Requests
IRQE	1	I	Edge-Sensitive Interrupt
			Request
BR	1	I	Bus Request Input
BG	1	O	Bus Grant Output
BGH	1	O	Bus Grant Hung Output
PMS	1	O	Program Memory Select Output
DMS	1	O	Data Memory Select Output
BMS	1	O	Byte Memory Select Output
IOMS	1	O	I/O Space Memory Select Output
CMS	1	O	Combined Memory Select Output
RD	1	O	Memory Read Enable Output
WR	1	O	Memory Write Enable Output
MMAP	1	I	Memory Map Select Input
BMODE	1	I	Boot Option Control Input
CLKIN,
XTAL	2	I	Clock or Quartz Crystal Input

	#
Pin	of	Input/
Name(s)	Pins	Output	Function
CLKOUT	1	O	Processor Clock Output
SPORT0	5	I/O	Serial Port I/O Pins
SPORT1	5	I/O	Serial Port 1 or Two External
			IRQs, Flag In and Flag Out
IRD, IWR	2	I	IDMA Port Read/Write Inputs
IS	1	I	IDMA Port Select
IAL	1	I	IDMA Port Address Latch
			Enable
IAD	16	I/O	IDMA Port Address/Data Bus
IACK	1	O	IDMA Port Access Ready
			Acknowledge
PWD	1	I	Power-Down Control
PWDACK	1	O	Power-Down Control
FL0, FL1,
FL2	3	O	Output Flags
PF7:0	8	I/O	Programmable I/O Pins
EE	1	*	(Emulator Only*)
EBR	1	*	(Emulator Only*)
EBG	1	*	(Emulator Only*)
ERESET	1	*	(Emulator Only*)
EMS	1	*	(Emulator Only*)
EINT	1	*	(Emulator Only*)
ECLK	1	*	(Emulator Only*)
ELIN	1	*	(Emulator Only*)
ELOUT	1	*	(Emulator Only*)
GND	11	–	Ground Pins
VDD	6	–	Power Supply Pins

*These ADSP-2181 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors.

Interrupts

The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead.

The ADSP-2181 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and

FLAG_OUT, for a total of six external interrupts. The ADSP2181 also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software and the power-down control circuit. The interrupt levels are internally prioritized and

individually maskable (except power down and reset). The IRQ2, IRQ0 and IRQ1 input pins can be programmed to be either levelor edge-sensitive. IRQL0 and IRQL1 are level-

sensitive and IRQE is edge sensitive. The priorities and vector addresses of all interrupts are shown in Table I.

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Table I. Interrupt Priority and Interrupt Vector Addresses

	Interrupt Vector
Source of Interrupt	Address (Hex)
Reset (or Power-Up with PUCR = 1)	0000	(Highest Priority)
Power-Down (Nonmaskable)	002C
IRQ2	0004
IRQL1	0008
IRQL0	000C
SPORT0 Transmit	0010
SPORT0 Receive	0014
IRQE	0018
BDMA Interrupt	001C
SPORT1 Transmit or IRQ1	0020
SPORT1 Receive or IRQ0	0024	(Lowest Priority)
Timer	0028

Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable.

The ADSP-2181 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to

be either edgeor level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear interrupts.

On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop and subroutine nesting.

The following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2181 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are:

•Power-Down

•Idle

•Slow Idle

The CLKOUT pin may also be disabled to reduce external power dissipation.

Power-Down

The ADSP-2181 processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. Here is a brief list of powerdown features. For detailed information about the powerdown feature, refer to the ADSP-2100 Family User’s Manual,

Third Edition, “System Interface” chapter.

•Quick recovery from power-down. The processor begins executing instructions in as few as 100 CLKIN cycles.

•Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 100 CLKIN cycle recovery.

•Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 100 CLKIN cycle start up.

•Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit.

•Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt.

•Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state.

•The RESET pin also can be used to terminate powerdown.

•Power-down acknowledge pin indicates when the processor has entered power-down.

Idle

When the ADSP-2181 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction.

Slow Idle

The IDLE instruction is enhanced on the ADSP-2181 to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction.

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ADSP-2181

When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2181 will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64 or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles).

SYSTEM INTERFACE

Figure 2 shows a typical basic system configuration with the ADSP-2181, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories. Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSP-2181 also provides four external interrupts and two serial ports or six external interrupts and one serial port.

		ADSP-2181
1/2x CLOCK		CLKIN	14	A13-0
OR		XTAL	ADDR13-0
CRYSTAL				D23-16	A0-A21
		FL0-2	24	D15-8		BYTE
		PF0-7				MEMORY
			DATA23-0		DATA
		IRQ2
		IRQE	BMS		CS
		IRQL0
			RD	A10-0
		IRQL1
		SPORT1	WR	D23-8	ADDR
						I/O SPACE
		SCLK1			DATA
SERIAL		RFS1 OR IRQ0			(PERIPHERALS)
		TFS1 OR IRQ1	IOMS		CS	2048 LOCATIONS
DEVICE
		DT1 OR FO
		DR1 OR FI		A13-0
		SPORT0		D23-0	ADDR	OVERLAY
						MEMORY
		SCLK0			DATA
SERIAL		RFS0				TWO 8K
		TFS0	PMS
DEVICE						PM SEGMENTS
		DT0
			DMS
		DR0
			CMS			TWO 8K
		IDMA PORT				DM SEGMENTS
			BR
		IRD
SYSTEM			BG
		IWR
			BGH
INTERFACE		IS
OR		IAL	PWD
mCONTROLLER	16	IACK	PWDACK
		IAD15-0

Figure 2. ADSP-2181 Basic System Configuration

Clock Signals

The ADSP-2181 can be clocked by either a crystal or a TTLcompatible clock signal.

The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9,

ADSP-2100 Family User’s Manual, Third Edition, for detailed information on this power-down feature.

If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected.

The ADSP-2181 uses an input clock with a frequency equal to half the instruction rate; a 20.00 MHz input clock yields a 25 ns processor cycle (which is equivalent to 40 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled.

Because the ADSP-2181 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.

A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.

CLKIN			XTAL		CLKOUT

DSP

Figure 3. External Crystal Connections

Reset

The RESET signal initiates a master reset of the ADSP-2181. The RESET signal must be asserted during the power-up se-

quence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does

not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the mini-

mum pulse width specification, tRSP.

The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an

external Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.

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Memory Architecture

The ADSP-2181 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O.

Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2181 has 16K words of Program Memory RAM on chip and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. Both an instruction opcode and a data value can be read from on-chip program memory in a single cycle.

Data Memory is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2181 has 16K words on Data Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memorymapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus.

Byte Memory provides access to an 8-bit wide memory space through the Byte DMA (BDMA) port. The Byte Memory interface provides access to 4 MBytes of memory by utilizing eight data lines as additional address lines. This gives the BDMA Port an effective 22-bit address range. On power-up, the DSP can automatically load bootstrap code from byte memory.

I/O Space allows access to 2048 locations of 16-bit-wide data. It is intended to be used to communicate with parallel peripheral devices such as data converters and external registers or latches.

Program Memory

The ADSP-2181 contains a 16K × 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2181 allows the use of 8K external memory overlays.

The program memory space organization is controlled by the MMAP pin and the PMOVLAY register. Normally, the ADSP2181 is configured with MMAP = 0 and program memory organized as shown in Figure 4.

PROGRAM MEMORY ADDRESS

0x3FFF

8K INTERNAL

(PMOVLAY = 0, MMAP = 0)

OR

EXTERNAL 8K

(PMOVLAY = 1 or 2, MMAP = 0)

0x2000

0x1FFF

8K INTERNAL

0x0000

Figure 4. Program Memory (MMAP = 0)

There are 16K words of memory accessible internally when the PMOVLAY register is set to 0. When PMOVLAY is set to something other than 0, external accesses occur at addresses 0x2000 through 0x3FFF. The external address is generated as shown in Table II.

Table II.

PMOVLAY	Memory	A13	A12:0
0	Internal	Not Applicable	Not Applicable
1	External	0	13 LSBs of Address
	Overlay 1		Between 0x2000
			and 0x3FFF
2	External	1	13 LSBs of Address
	Overlay 2		Between 0x2000
			and 0x3FFF

This organization provides for two external 8K overlay segments using only the normal 14 address bits. This allows for simple program overlays using one of the two external segments in place of the on-chip memory. Care must be taken in using this overlay space in that the processor core (i.e., the sequencer) does not take into account the PMOVLAY register value. For example, if a loop operation was occurring on one of the external overlays and the program changes to another external overlay or internal memory, an incorrect loop operation could occur. In addition, care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack.

For ADSP-2100 Family compatibility, MMAP = 1 is allowed. In this mode, booting is disabled and overlay memory is disabled (PMOVLAY must be 0). Figure 5 shows the memory map in this configuration.

PROGRAM MEMORY ADDRESS

0x3FFF

INTERNAL 8K

(PMOVLAY = 0, MMAP = 1)

0x2000

0x1FFF

8K EXTERNAL

0x0000

Figure 5. Program Memory (MMAP = 1)

Data Memory

The ADSP-2181 has 16,352 16-bit words of internal data memory. In addition, the ADSP-2181 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory.

DATA MEMORY

ADDRESS

0x3FFF

32 MEMORY–

MAPPED REGISTERS

0x3FEO

0x3FDF

INTERNAL 8160 WORDS

0x2000

0x1FFF

8K INTERNAL (DMOVLAY = 0)

OR

EXTERNAL 8K

(DMOVLAY = 1, 2)

0x0000

Figure 6. Data Memory

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ADSP-2181

There are 16,352 words of memory accessible internally when the DMOVLAY register is set to 0. When DMOVLAY is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as shown in Table III.

Table III.

DMOVLAY	Memory	A13	A12:0
0	Internal	Not Applicable	Not Applicable
1	External	0	13 LSBs of Address
	Overlay 1		Between 0x0000
			and 0x1FFF
2	External	1	13 LSBs of Address
	Overlay 2		Between 0x0000
			and 0x1FFF

This organization allows for two external 8K overlays using only the normal 14 address bits.

All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register.

I/O Space

The ADSP-2181 supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals or to bus interface ASIC data registers. I/O space supports 2048 locations. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0-3, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table IV.

Table IV.

Address Range

Wait State Register

0x000–0x1FF IOWAIT0 0x200–0x3FF IOWAIT1 0x400–0x5FF IOWAIT2 0x600–0x7FF IOWAIT3

Composite Memory Select (CMS)

The ADSP-2181 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated

to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their

functionality.

When set, each bit in the CMSSEL register, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory; use either DMS or PMS as the additional address bit.

The CMS pin functions like the other memory select signals, with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits, except the BMS bit, default to 1 at reset.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K × 8.

The byte memory space on the ADSP-2181 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register.

Byte Memory DMA (BDMA)

The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally, and steals only one DSP cycle per 8-, 16or 24-bit word transferred.

The BDMA circuit supports four different data formats which are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table V shows the data formats supported by the BDMA circuit.

Table V.

	Internal
BTYPE	Memory Space	Word Size	Alignment
00	Program Memory	24	Full Word
01	Data Memory	16	Full Word
10	Data Memory	8	MSBs
11	Data Memory	8	LSBs

Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be on-chip program or data memory, regardless of the values of MMAP, PMOVLAY or DMOVLAY.

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ADSP-2181

When the BWCOUNT register is written with a nonzero value, the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor and start execution at address 0 when the BDMA accesses have completed.

Internal Memory DMA Port (IDMA Port)

The IDMA Port provides an efficient means of communication between a host system and the ADSP-2181. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’s memorymapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP-2181 is operating at full speed.

The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access.

IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location; the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register.

Once the address is stored, data can either be read from or written to the ADSP-2181’s on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2181 that a particular transaction is required. In either case, there is a one-processor- cycle delay for synchronization. The memory access consumes one additional processor cycle.

Once an access has occurred, the latched address is automatically incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation.

Bootstrap Loading (Booting)

The ADSP-2181 has two mechanisms to allow automatic loading of the on-chip program memory after reset. The method for booting after reset is controlled by the MMAP and BMODE pins as shown in Table VI.

Table VI. Boot Summary Table

MMAP	BMODE	Booting Method
0	0	BDMA feature is used in default mode
		to load the first 32 program memory
		words from the byte memory space.
		Program execution is held off until all
		32 words have been loaded.
0	1	IDMA feature is used to load any inter-
		nal memory as desired. Program execu-
		tion is held off until internal program
		memory location 0 is written to.
1	X	Bootstrap features disabled. Program
		execution immediately starts from
		location 0.

BDMA Booting

When the BMODE and MMAP pins specify BDMA booting (MMAP = 0, BMODE = 0), the ADSP-2181 initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24 bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0.

The ADSP-2100 Family Development Software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface.

IDMA Booting

The ADSP-2181 can also boot programs through its Internal DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2181 boots from the IDMA port. IDMA feature can load as much onchip memory as desired. Program execution is held off until onchip program memory location 0 is written to.

The ADSP-2100 Family Development Software (Revision 5.02 and later) can generate IDMA compatible boot code.

Bus Request and Bus Grant

The ADSP-2181 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-2181 is not performing an external memory access, then it responds to the active BR input in the following processor cycle by:

•three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers,

•asserting the bus grant (BG) signal, and

•halting program execution.

REV. D

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ADSP-2181

If Go Mode is enabled, the ADSP-2181 will not halt program execution until it encounters an instruction that requires an external memory access.

If the ADSP-2181 is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses.

When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point where it stopped.

The bus request feature operates at all times, including when the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2181 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2181 deasserts BG and BGH and executes the external memory access.

Flag I/O Pins

The ADSP-2181 has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2181’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2181 has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1.

INSTRUCTION SET DESCRIPTION

The ADSP-2181 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the following benefits:

•The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation.

•Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle.

•The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP2181’s interrupt vector and reset vector map.

•Sixteen condition codes are available. For conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle.

•Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2181 has on-chip emulation support and an ICEPort, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE ’s in-circuit probe, a 14-pin plug.

The ICE-Port interface consists of the following ADSP-2181 pins:

EBR	EMS	ELIN
EBG	EINT	ELOUT
ERESET	ECLK	EE

These ADSP-2181 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the ADSP2181 and the connector must be kept as short as possible, no longer than three inches.

The following pins are also used by the EZ-ICE:

BR	BG
GND	RESET

The EZ-ICE uses the EE (emulator enable) signal to take con-

trol of the ADSP-2181 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated.

These signals do not need to be jumper-isolated in your system.

The EZ-ICE connects to the target system via a ribbon cable and a 14-pin female plug. The ribbon cable is 10 inches in length with one end fixed to the EZ-ICE. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in Figure 7. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector.

		1		2
	GND						BG
		3		4
	EBG						BR
		5		6
	EBR						EINT
		7		8
	KEY (NO PIN)						ELIN
		9		10
	ELOUT						ECLK
		11		12
	EE						EMS
		13		14
	RESET						ERESET

TOP VIEW

Figure 7. Target Board Connector for EZ-ICE

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REV. D