Analog Devices AD724 Datasheet

a

RGB to NTSC/PAL Encoder

AD724

FEATURES

Low Cost, Integrated Solution +5 V Operation

Accepts FSC Clock or Crystal, or 4FSC Clock Composite Video and Separate Y/C (S-Video) Outputs Luma and Chroma Outputs Are Time Aligned Minimal External Components:

No External Filters or Delay Lines Required Onboard DC Clamp

Accepts Either HSYNC and VSYNC or CSYNC Phase Lock to External Subcarrier

Drives 75 V Reverse-Terminated Loads

Logic Selectable NTSC or PAL Encoding Modes Compact 16-Lead SOIC

APPLICATIONS

RGB to NTSC or PAL Encoding

PRODUCT DESCRIPTION

The AD724 is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chrominance (subcarrier amplitude and phase) signals in accordance with either NTSC or PAL standards. These two outputs are also combined to provide composite video output. All three outputs can simultaneously drive 75 Ω, reverse-terminated cables. All logical inputs are TTL, 3 V and 5 V CMOS compatible. The chip

operates from a single +5 V supply. No external delay lines or filters are required. The AD724 may be powered down when not in use.

The AD724 accepts either FSC or 4FSC clock. When a clock is not available, a low cost parallel-resonant crystal (3.58 MHz (NTSC) or 4.43 MHz (PAL)) and the AD724’s on-chip oscillator generate the necessary subcarrier clock. The AD724 also accepts the subcarrier clock from an external video source.

The interface to graphics controllers is simple: an on-chip logic “XNOR” accepts the available vertical (VSYNC) and horizontal sync (HSYNC) signals and creates the composite sync (CSYNC) signal on-chip. If available, the AD724 will also accept a standard CSYNC signal by connecting VSYNC to Logic HI and applying CSYNC to the HSYNC pin. The AD724 contains decoding logic to identify valid horizontal sync pulses for correct burst insertion.

Delays in the U and V chroma filters are matched by an on-chip sampled-data delay line in the Y signal path. To prevent aliasing, a prefilter at 5 MHz is included ahead of the delay line and a post-filter at 5 MHz is added after the delay line to suppress harmonics in the output. These low-pass filters are optimized for minimum pulse overshoot. The overall luma delay, relative to chroma, has been designed to be time aligned for direct input to a television’s baseband. The AD724 comes in a space-saving SOIC and is specified for the 0°C to +70°C commercial temperature range.

					FUNCTIONAL BLOCK DIAGRAM
				PHASE
	FSC		DETECTOR			LOOP	4FSC
SUB-			XOSC		CHARGE
CARRIER					PUMP	FILTER	VCO
	4FSC	4FSC			FSC
NTSC/PAL			SYNC		CSYNC
HSYNC		XNOR	SEPARATOR		BURST	NTSC/PAL
VSYNC
			CSYNC
						±180°
			QUADRATURE		FSC 90°		SC 90°/270°
		4FSC				(PAL ONLY)
			+4		FSC 0°
			DECODER
							CLOCK
					CSYNC		AT 8FSC
		DC		Y	3-POLE		SAMPLED-	2-POLE	X2	LUMINANCE
RED					LP PRE-		DATA	LP POST-
		CLAMP								OUTPUT
					FILTER		DELAY LINE	FILTER
			RGB-TO-YUV					NTSC/PAL	X2	COMPOSITE
		DC		U	4-POLE	U				OUTPUT
GREEN			ENCODING
		CLAMP			LPF	CLAMP
			MATRIX
							BALANCED	4-POLE
									X2	CHROMINANCE
							MODULATORS	LPF		OUTPUT
BLUE		DC		V	4-POLE	V
		CLAMP			LPF	CLAMP
					BURST

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 1999

AD724–SPECIFICATIONS	(Unless otherwise noted, VS = +5, TA = +258C, using FSC synchronous clock. All loads are
	150 V 6 5% at the IC pins. Outputs are measured at the 75 V reverse terminated load.)
Parameter		Conditions	Min	Typ	Max	Units
SIGNAL INPUTS (RIN, GIN, BIN)
Input Amplitude		Full Scale			714	mV p-p
Black Level1				0.8		V
Input Resistance2		RIN, GIN, BIN	1			MΩ
Input Capacitance				5		pF
LOGIC INPUTS (HSYNC, VSYNC, FIN, ENCD, STND, SELECT)		CMOS Logic Levels
Logic LO Input Voltage					1	V
Logic HI Input Voltage			2			V
Logic LO Input Current (DC)				<1		µA
Logic HI Input Current (DC)				<1		µA
VIDEO OUTPUTS3
Luminance (LUMA)
Roll-Off @ 5 MHz		NTSC		–7		dB
		PAL		–6		dB
Gain Error			–15	–3	+15	%
Nonlinearity				± 0.3		%
Sync Level		NTSC	243	286	329	mV
		PAL		300		mV
DC Black Level				1.3		V
Chrominance (CRMA)
Bandwidth		NTSC		3.6		MHz
		PAL		4.4		MHz
Color Burst Amplitude		NTSC	170	249	330	mV p-p
		PAL		288		mV
Color Signal to Burst Ratio Error4				± 5		%
Color Burst Width		NTSC		2.51		µs
		PAL		2.28		µs
Phase Error5				± 3		Degrees
DC Black Level				2.0		V
Chroma Feedthrough		R, G, B = 0		15	40	mV p-p
Composite (COMP)				± 1
Absolute Gain Error		With Respect to Luma	–5		5	%
Differential Gain		With Respect to Chroma		0.5		%
Differential Phase		With Respect to Chroma		2.0		Degrees
DC Black Level				1.5		V
Chroma/Luma Time Alignment				0		ns
POWER SUPPLIES
Recommended Supply Range		Single Supply	+4.75		+5.25	V
Quiescent Current—Encode Mode6				33	42	mA
Quiescent Current—Power Down				1		mA

NOTES

1R, G, and B signals are inputted via an external ac coupling capacitor. 2Except during dc restore period (back porch clamp).

3All outputs measured at a 75 Ω reverse-terminated load; ac voltages at the IC output pins are twice those specified here. 4Ratio of chroma amplitude to burst amplitude, difference from ideal.

5Difference between ideal color-bar phases and the actual values.

6Driving the logic inputs with VOH < 4 V will increase static supply current approximately 150 µA per input.

Specifications are subject to change without notice.

–2–

REV. B

AD724

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage, APOS to AGND . . . . . . . . .		. . . . . . . . . +6 V
Supply Voltage, DPOS to DGND . . . . . . . . .		. . . . . . . . . +6 V
AGND to DGND . . . . . . . .	. . . . . . . . . . . . .	–0.3 V to +0.3 V
Inputs . . . . . . . . . . . . . . . . .	DGND – 0.3 V to DPOS + 0.3 V
Internal Power Dissipation . . .	. . . . . . . . . . . .	. . . . . . . 800 mW
Operating Temperature Range . . . . . . . . . . .		. . 0°C to +70°C
Storage Temperature Range .	. . . . . . . . . . . .	–65°C to +125°C
Lead Temperature Range (Soldering 30 sec) .		. . . . . . . +230°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Thermal Characteristics: 16-Lead SOIC Package: θJA = 100°C/W.

PIN CONFIGURATION 16-Lead Wide Body (SOIC) (R-16)

STND				HSYNC
	1		16
AGND				VSYNC
	2		15
FIN				DPOS
	3		14
		AD724		DGND
APOS	4		13
ENCD		TOP VIEW		SELECT
	5	(Not to Scale)	12
RIN				LUMA
	6		11
GIN				COMP
	7		10
BIN				CRMA
	8		9

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Option
AD724JR	0°C to +70°C	16-Lead SOIC	R-16
AD724JR-REEL	0°C to +70°C	16-Lead SOIC	R-16
AD724JR-REEL7	0°C to +70°C	16-Lead SOIC	R-16
AD724-EB		Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD724 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–3–

AD724

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Description

Equivalent Circuit

1

STND

A Logical HIGH input selects NTSC encoding.

Circuit A

A Logical LOW input selects PAL encoding.

CMOS/TTL Logic Levels.

2

AGND

Analog Ground Connection.

3

FIN

FSC clock or parallel-resonant crystal, or 4FSC clock input.

Circuit B

For NTSC: 3.579 545 MHz or 14.318 180 MHz.

For PAL: 4.433 619 MHz or 17.734 480 MHz.

CMOS/TTL Logic Levels for subcarrier clocks.

4

APOS

Analog Positive Supply (+5 V ± 5%).

5

ENCD

A Logical HIGH input enables the encode function.

Circuit A

A Logical LOW input powers down chip when not in use.

CMOS/TTL Logic Levels.

6

RIN

Red Component Video Input.

Circuit C

0 to 714 mV AC-Coupled.

7

GIN

Green Component Video Input.

Circuit C

0 to 714 mV AC-Coupled.

8

BIN

Blue Component Video Input.

Circuit C

0 to 714 mV AC-Coupled.

9

CRMA

Chrominance Output.*

Circuit D

Approximately 1.8 V peak-to-peak for both NTSC and PAL.

10

COMP

Composite Video Output.*

Circuit D

Approximately 2.5 V peak-to-peak for both NTSC and PAL.

11

LUMA

Luminance plus SYNC Output.*

Circuit D

Approximately 2 V peak-to-peak for both NTSC and PAL.

12

SELECT

A Logical LOW input selects the FSC operating mode.

Circuit A

A Logical HIGH input selects the 4FSC operating mode.

CMOS/TTL Logic Levels.

13

DGND

Digital Ground Connections.

14

DPOS

Digital Positive Supply (+5 V ± 5%).

15

VSYNC

Vertical Sync Signal (if using external CSYNC set at > +2 V). CMOS/TTL Logic Levels.

Circuit A

16

HSYNC

Horizontal Sync Signal (or CSYNC signal). CMOS/TTL Logic Levels.

Circuit A

*The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75 Ω reverse-terminated lines.

DPOS

DPOS

1

5

6

7

12

DGND

8

DGND

15

VCLAMP

16

Circuit A

Circuit C

DPOS

APOS

DPOS

3

9

10

VBIAS

11

DGND

AGND

DGND

Circuit B

Circuit D

Equivalent Circuits

–4–

REV. B

Typical Performance Characteristics–AD724

		COMPOSITE			+5V
TEKTRONIX		SYNC			AD724
TSG 300							COMPOSITE	SONY
COMPONENT					RGB TO		VIDEO	MONITOR
VIDEO		RGB			NTSC/PAL			MODEL
WAVEFORM					ENCODER			1342
GENERATOR		3
			75V			FIN
	GENLOCK
									75V
TEKTRONIX
1910		FSC						TEKTRONIX
COMPOSITE
VIDEO								VM700A
WAVEFORM								WAVEFORM
GENERATOR								MONITOR

Figure 1. Evaluation Setup

1.0	APL = 49.8%
	525 LINE NTSC	NO FILTERING
	SLOW CLAMP TO 0.00V					100
	@ 6.63ms
0.5
VOLTS						50
						IRE
0.0						0
	SYNCHRONOUS			SYNC = SOURCE
			FRAMES SELECTED : 1 2			–50
–0.5	10	20	30	40	50	60
0
			ms

Figure 2. Modulated Pulse and Bar, NTSC

1.0
	APL = 50.0%
	625 LINE PAL	NO FILTERING
	SLOW CLAMP TO 0.00V @ 6.72ms
0.5
VOLTS
0.0
		ASYNCHRONOUS			SYNC = SOURCE
			FRAMES SELECTED : 1 2 3 4
–0.5	10	20	30	40	50	60
0
			ms

1.0			APL = 50.8%
			525 LINE NTSC		NO FILTERING
			SLOW CLAMP TO 0.00V @ 6.63ms
						100
0.5
VOLTS						50
						IRE
0.0						0
	PRECISION MODE OFF
		SYNCHRONOUS		SYNC = SOURCE		–50
			FRAMES SELECTED : 1 2
–0.5	10	20	30	40	50	60
0
			ms
	Figure 4. 100% Color Bars, NTSC
1.0			APL = 50.6%
			625 LINE PAL		NO FILTERING
			SLOW CLAMP TO 0.00V @ 6.72ms
0.5
VOLTS
0.0
		ASYNCHRONOUS		SYNC = SOURCE
			FRAMES SELECTED : 1 2 3 4
–0.5	10	20	30	40	50	60
0

ms

Figure 3. Modulated Pulse and Bar, PAL

Figure 5. 100% Color Bars, PAL

REV. B

–5–