Analog Devices AD7225UE, AD7225TQ, AD7225TE, AD7225LR, AD7225LP Datasheet

a LC2MOS Quad 8-Bit DAC

with Separate Reference Inputs

AD7225

FEATURES

Four 8-Bit DACs with Output Amplifiers Separate Reference Input for Each DAC

mP Compatible with Double-Buffered Inputs

Simultaneous Update of All Four Outputs Operates with Single or Dual Supplies Extended Temperature Range Operation No User Trims Required

Skinny 24-Pin DIP, SOIC and 28-Terminal Surface Mount Packages

GENERAL DESCRIPTION

The AD7225 contains four 8-bit voltage output digital-to- analog converters, with output buffer amplifiers and interface logic on a single monolithic chip. Each D/A converter has a separate reference input terminal. No external trims are required to achieve full specified performance for the part.

The double-buffered interface logic consists of two 8-bit registers per channel–an input register and a DAC register. Control inputs A0 and A1 determine which input register is loaded when WR goes low. Only the data held in the DAC registers determines the analog outputs of the converters. The doublebuffering allows simultaneous update of all four outputs under control of LDAC. All logic inputs are TTL and CMOS (5 V) level compatible and the control logic is speed compatible with most 8-bit microprocessors.

Specified performance is guaranteed for input reference voltages from +2 V to +12.5 V when using dual supplies. The part is also specified for single supply operation using a reference of +10 V. Each output buffer amplifier is capable of developing +10 V across a 2 kΩ load.

The AD7225 is fabricated on an all ion-implanted high-speed Linear Compatible CMOS (LC2MOS) process which has been specifically developed to integrate high speed digital logic circuits and precision analog circuitry on the same chip.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1.DACs and Amplifiers on CMOS Chip

The single-chip design of four 8-bit DACs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all analog inputs and outputs at one end of the package and all digital inputs at the other.

2.Single or Dual Supply Operation

The voltage-mode configuration of the AD7225 allows single supply operation. The part can also be operated with dual supplies giving enhanced performance for some parameters.

3.Versatile Interface Logic

The AD7225 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. The double-buffered interface allows simultaneous update of the four outputs.

4.Separate Reference Input for Each DAC

The AD7225 offers great flexibility in dealing with input signals with a separate reference input provided for each DAC and each reference having variable input voltage capability.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] Fax: [phone]

AD7225–SPECIFICATIONS

DUAL SUPPLY	(VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted.
	All specifications TMIN to TMAX unless otherwise noted.)
		K, B	L, C
Parameter		Versions2	Versions2	T Version	U Version	Units	Conditions/Comments
STATIC PERFORMANCE
Resolution		8	8	8	8	Bits
Total Unadjusted Error		± 2	± 1	± 2	± 1	LSB max	VDD = +15 V ± 5%, VREF = +10 V
Relative Accuracy		± 1	± 1/2	± 1	± 1/2	LSB max
Differential Nonlinearity		± 1	± 1	± 1	± 1	LSB max	Guaranteed Monotonic
Full-Scale Error		± 1	± 1/2	± 1	± 1/2	LSB max
Full-Scale Temp. Coeff.		± 5	± 5	± 5	± 5	ppm/°C typ	VDD = 14 V to 16.5 V, VREF = +10 V
Zero Code Error @ 25°C		± 25	± 15	± 25	± 15	mV max
TMIN to TMAX		± 30	± 20	± 30	± 20	mV max
Zero Code Error Temp Coeff.		± 30	± 30	± 30	± 30	μV/°C typ
REFERENCE INPUT
Voltage Range		2 to (VDD – 4)	2 to (VDD – 4)	2 to (VDD – 4)	2 to (VDD – 4)	V min to V max
Input Resistance		11	11	11	11	kΩ min
Input Capacitance3		100	100	100	100	pF max	Occurs when each DAC is loaded with all 1s.
Channel-to-Channel Isolation3		60	60	60	60	dB min	VREF = 10 V p-p Sine Wave @ 10 kHz
AC Feedthrough3		–70	–70	–70	–70	dB max	VREF = 10 V p-p Sine Wave @ 10 kHz
DIGITAL INPUTS
Input High Voltage, VINH		2.4	2.4	2.4	2.4	V min
Input Low Voltage, VINL		0.8	0.8	0.8	0.8	V max
Input Leakage Current		± 1	± 1	± 1	± 1	μA max	VIN = 0 V or VDD
Input Capacitance3		8	8	8	8	pF max
Input Coding		Binary	Binary	Binary	Binary
DYNAMIC PERFORMANCE						V/μs min
Voltage Output Slew Rate3		2.5	2.5	2.5	2.5
Voltage Output Settling Time3						μs max	VREF = +10 V; Settling Time to ± 1/2 LSB
Positive Full-Scale Change		5	5	5	5
Negative Full-Scale Change		5	5	5	5	μs max	VREF = +10 V; Settling Time to ± 1/2 LSB
Digital Feedthrough3		50	50	50	50	nV secs typ	Code transition all 0s to all 1s.
Digital Crosstalk3		50	50	50	50	nV secs typ	Code transition all 0s to all 1s.
Minimum Load Resistance		2	2	2	2	kΩ min	VOUT = +10 V
POWER SUPPLIES
VDD Range		11.4/16.5	11.4/16.5	11.4/16.5	11.4/16.5	V min to V max	For Specified Performance
IDD		10	10	12	12	mA max	Outputs Unloaded; VIN = VINL or VINH
ISS		9	9	10	10	mA max	Outputs Unloaded; VIN = VINL or VINH
SWITCHING CHARACTERISTICS3, 4
t1
@ 25°C		95	95	95	95	ns min	Write Pulse Width
TMIN to TMAX		120	120	150	150	ns min
t2
@ 25°C		0	0	0	0	ns min	Address to Write Setup Time
TMIN to TMAX		0	0	0	0	ns min
t3
@ 25°C		0	0	0	0	ns min	Address to Write Hold Time
TMIN to TMAX		0	0	0	0	ns min
t4
@ 25°C		70	70	70	70	ns min	Data Valid to Write Setup Time
TMIN to TMAX		90	90	90	90	ns min
t5
@ 25°C		10	10	10	10	ns min	Data Valid to Write Hold Time
TMIN to TMAX		10	10	10	10	ns min
t6
@ 25°C		95	95	95	95	ns min	Load DAC Pulse Width
TMIN to TMAX		120	120	150	150	ns min

NOTES

1Maximum possible reference voltage.

2Temperature ranges are as follows: K, L Versions: –40°C to +85°C B, C Versions: –40°C to +85°C T, U Versions: –55°C to +125°C

3Sample Tested at 25°C to ensure compliance.

4Switching characteristics apply for single and dual supply operation.

Specifications subject to change without notice.

–2–

REV. B

AD7225

(VDD = +15 V 6 5%; VSS = AGND = DGND = O V; VREF = +10 V1 unless otherwise noted.
SINGLE SUPPLY All specifications TMIN to TMAX unless otherwise noted.)
			K, B	L, C
Parameter			Versions2	Versions2	T Version	U Version	Units	Conditions/Comments
STATIC PERFORMANCE
Resolution			8	8	8	8	Bits
Total Unadjusted Error3			± 2	± 1	± 2	± 1	LSB max
Differential Nonlinearity3			± 1	± 1	± 1	± 1	LSB max	Guaranteed Monotonic
REFERENCE INPUT							kΩ min
Input Resistance			11	11	11	11
Input Capacitance4			100	100	100	100	pF max	Occurs when each DAC is loaded with all 1s.
Channel-to-Channel Isolation3, 4			60	60	60	60	dB min	VREF = 10 V p-p Sine Wave @ 10 kHz
AC Feedthrough3, 4, 5			–70	–70	–70	–70	dB max	VREF = 10 V p-p Sine Wave @ 10 kHz
DIGITAL INPUTS
Input High Voltage, VINH			2.4	2.4	2.4	2.4	V min
Input Low Voltage, VINL			0.8	0.8	0.8	0.8	V max
Input Leakage Current			± 1	± 1	± 1	± 1	μA max	VIN = 0 V or VDD
Input Capacitance4			8	8	8	8	pF max
Input Coding			Binary	Binary	Binary	Binary
DYNAMIC PERFORMANCE							V/μs min
Voltage Output Slew Rate4			2	2	2	2
Voltage Output Settling Time4							μs max	Settling Time to ±1/2 LSB
Positive Full-Scale Change			5	5	5	5
Negative Full-Scale Change			7	7	7	7	μs max	Settling Time to ±1/2 LSB
Digital Feedthrough3, 4			50	50	50	50	nV secs typ	Code transition all 0s to all 1s.
Digital Crosstalk3, 4			50	50	50	50	nV secs typ	Code transition all 0s to all 1s.
Minimum Load Resistance			2	2	2	2	kΩ min	VOUT = +10 V
POWER SUPPLIES
VDD Range			14.25/15.75	14.25/15.75	14.25/15.75	14.25/15.75	V min to V max	For Specified Performance
IDD			10	10	12	12	mA max	Outputs Unloaded; VIN = VINL or VINH
SWITCHING CHARACTERISTICS		4
t1
@ 25°C			95	95	95	95	ns min	Write Pulse Width
TMIN to TMAX			120	120	150	150	ns min
t2
@ 25°C			0	0	0	0	ns min	Address to Write Setup Time
TMIN to TMAX			0	0	0	0	ns min
t3
@ 25°C			0	0	0	0	ns min	Address to Write Hold Time
TMIN to TMAX			0	0	0	0	ns min
t4
@ 25°C			70	70	70	70	ns min	Data Valid to Write Setup Time
TMIN to TMAX			90	90	90	90	ns min
t5
@ 25°C			10	10	10	10	ns min	Data Valid to Write Hold Time
TMIN to TMAX			10	10	10	10	ns min
t6
@ 25°C			95	95	95	95	ns min	Load DAC Pulse Width
TMIN to TMAX			120	120	150	150	ns min

NOTES

1Maximum possible reference voltage.

2Temperature ranges are as follows: K, L Versions: –40°C to +85°C B, C Versions: –40°C to +85°C T, U Versions: –55°C to +125°C

3Sample Tested at 25°C to ensure compliance.

4Switching characteristics apply for single and dual supply operation.

Specifications subject to change without notice.

ORDERING GUIDE

		Total
	Temperature	Unadjusted	Package
Model1	Range	Error	Option2
AD7225KN	–40°C to +85°C	±2 LSB	N-24
AD7225LN	–40°C to +85°C	±1 LSB	N-24
AD7225KP	–40°C to +85°C	±2 LSB	P-28A
AD7225LP	–40°C to +85°C	±1 LSB	P-28A
AD7225KR	–40°C to +85°C	±2 LSB	R-24
AD7225LR	–40°C to +85°C	±1 LSB	R-24
AD7225BQ	–40°C to +85°C	±2 LSB	Q-24
AD7225CQ	–40°C to +85°C	±1 LSB	Q-24

		Total
	Temperature	Unadjusted	Package
Model1	Range	Error	Option2
AD7225TQ	–55°C to +125°C	±2 LSB	Q-24
AD7225UQ	–55°C to +125°C	±1 LSB	Q-24
AD7225TE	–55°C to +125°C	±2 LSB	E-28A
AD7225UE	–55°C to +125°C	±1 LSB	E-28A

NOTES

1To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet.

2E = Leadless Ceramic Chip Carrier; N = Plastic DIP;

P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.

REV. B

–3–

AD7225

ABSOLUTE MAXIMUM RATINGS1
VDD to AGND . . . . . . . . . . . . . . . . . . . . .	. . .	. . –0.3 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . .	. . .	. –0.3 V, +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . .	. . .	. –0.3 V, +24	V
AGND to DGND . . . . . . . . . . . . . . . . . . .	. . .	. . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . .	–0.3 V, VDD + 0.3		V
VREF to AGND . . . . . . . . . . . . . . . . . . . .	–0.3 V, VDD + 0.3		V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . .	. . .	. . . . . VSS, VDD
Power Dissipation (Any Package) to +75°C . . .		. . . . . 500 mW
Derates above 75°C by . . . . . . . . . . . . . . .	. . .	. . . 2.0 mW/°C
Operating Temperature		–40°C to +85°C
Commercial (K, L Versions) . . . . . . . . .	. .

Industrial (B, C Versions) . . . . . . . . . . . .	. –40°C to +85°C
Extended (T, U Versions) . . . . . . . . . . . .	–55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . .	–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . .	. . . . . . . +300°C

NOTES

1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Outputs may be shorted to any voltage in the range VSS to VDD provided that the power dissipation of the package is not exceeded. Typical short circuit current for a short to AGND or VSS is 50 mA.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7225 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

	PIN CONFIGURATIONS
DIP and SOIC	LCCC

WARNING!

ESD SENSITIVE DEVICE

PLCC

TERMINOLOGY

TOTAL UNADJUSTED ERROR

Total Unadjusted Error is a comprehensive specification which includes full-scale error, relative accuracy, and zero code error. Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB (ideal) is VREF/256. The LSB size will vary over the VREF range. Hence the zero code error will, relative to the LSB size, increase as VREF decreases. Accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of LSBs over the VREF range. As a result, total unadjusted error is specified for a fixed reference voltage of +10 V.

RELATIVE ACCURACY

Relative Accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero code error and full-scale error and is normally expressed in LSBs or as a percentage of full-scale reading.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB max over the operating temperature range ensures monotonicity.

DIGITAL FEEDTHROUGH

Digital Feedthrough is the glitch impulse transferred to the output of the DAC due to a change in its digital input code. It is specified in nV secs and is measured at VREF = 0 V.

DIGITAL CROSSTALK

Digital Crosstalk is the glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. It is specified in nV secs and is measured at VREF = 0 V.

AC FEEDTHROUGH

AC Feedthrough is the proportion of reference input signal which appears at the output of a converter when that DAC is loaded with all 0s.

CHANNEL-TO-CHANNEL ISOLATION

Channel-to-channel isolation is the proportion of input signal from the reference of one DAC (loaded with all 1s) which appears at the output of one of the other three DACs (loaded with all 0s) The figure given is the worst case for the three other outputs and is expressed as a ratio in dBs.

FULL-SCALE ERROR

Full-Scale Error is defined as:

Measured Value – Zero Code Error – Ideal Value

–4–

REV. B