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LC2MOS |
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Dual 12-Bit DACPORTs |
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AD7237A/AD7247A |
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FEATURES
Complete Dual 12-Bit DAC Comprising Two 12-Bit CMOS DACs
On-Chip Voltage Reference Output Amplifiers Reference Buffer Amplifiers
Improved AD7237/AD7247: 12 V to 15 V Operation
Faster Interface –30 ns typ Data Setup Time Parallel Loading Structure: AD7247A
(8+4) Loading Structure: AD7237A Single or Dual Supply Operation
Low Power—165 mW typ in Single Supply
GENERAL DESCRIPTION
The AD7237A/AD7247A is an enhanced version of the industry standard AD7237/AD7247. Improvements include operation from 12 V to 15 V supplies, faster interface times and better reference variations with VDD. Additional features include faster settling times.
The AD7237A/AD7247A is a complete, dual, 12-bit, voltage output digital-to-analog converter with output amplifiers and Zener voltage reference on a monolithic CMOS chip. No external user trims are required to achieve full specified performance.
Both parts are microprocessor compatible, with high speed data latches and interface logic. The AD7247A accepts 12-bit parallel data which is loaded into the respective DAC latch using the WR input and a separate Chip Select input for each DAC. The AD7237A has a double buffered interface structure and an 8-bit wide data bus with data loaded to the respective input latch in two write operations. An asynchronous LDAC signal on the AD7237A updates the DAC latches and analog outputs.
A REF OUT/REF IN function is provided which allows either the on-chip 5 V reference or an external reference to be used as a reference voltage for the part. For single supply operation, two output ranges of 0 V to +5 V and 0 V to +10 V are available, while these two ranges plus an additional ±5 V range are available with dual supplies. The output amplifiers are capable of developing +10 V across a 2 kΩ load to GND.
The AD7237A/AD7247A is fabricated in Linear Compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. Both parts are available in a 24-pin, 0.3" wide plastic and hermetic dual-in-line package (DIP) and are also packaged in a 24-lead small outline (SOIC) package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
PRODUCT HIGHLIGHTS
1.The AD7237A/AD7247A is a dual 12-bit DACPORT® on a single chip. This single chip design and small package size offer considerable space saving and increased reliability over multichip designs.
2.The improved interface times of the parts allow easy, direct interfacing to most modern microprocessors, whether they have 8-bit or 16-bit data bus structures.
3.The AD7237A/AD7247A features a wide power supply range allowing operation from 12 V supplies.
DACPORT is a registered trademark of Analog Devices, Inc.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7237A/AD7247A–SPECIFICATIONS(VDD = +12 V to +15 V,1 VSS = 0 V or –12 V to –15 V,1 AGND = DGND = 0 V [AD7237A], GND = 0 V [AD7247A], REF IN = +5 V,
RL = 2 kΩ, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
Parameter |
A2 |
B2 |
T2 |
Units |
Test Conditions/Comments |
STATIC PERFORMANCE |
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Resolution |
12 |
12 |
12 |
Bits |
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Relative Accuracy3 |
±1 |
±1/2 |
±1/2 |
LSB max |
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Differential Nonlinearity3 |
±0.9 |
±0.9 |
±0.9 |
LSB max |
Guaranteed Monotonic |
Unipolar Offset Error3 |
±3 |
±3 |
±4 |
LSB max |
VSS = 0 V or –12 V to –15 V4. DAC Latch Contents All 0s |
Bipolar Zero Error3 |
±6 |
±4 |
±6 |
LSB max |
VSS = –12 V to –15 V4. DAC Latch Contents |
Full-Scale Error3, 5 |
±5 |
±5 |
±6 |
LSB max |
1000 0000 0000 |
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Full-Scale Mismatch5 |
±1 |
±1 |
±1 |
LSB typ |
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REFERENCE OUTPUT |
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REF OUT |
4.97/5.03 |
4.97/5.03 |
4.95/5.05 |
V min/max |
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Reference Temperature |
±25 |
±25 |
±25 |
ppm/°C typ |
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Coefficient |
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Reference Load Change |
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Reference Load Current Change (0-100 μA) |
( REF OUT vs. I) |
–1 |
–1 |
–1 |
mV max |
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REFERENCE INPUT |
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5 V ± 5% |
Reference Input Range |
4.75/5.25 |
4.75/5.25 |
4.75/5.25 |
V min/max |
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Input Current6 |
±5 |
±5 |
±5 |
μA max |
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DIGITAL INPUTS |
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Input High Voltage, VINH |
2.4 |
2.4 |
2.4 |
V min |
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Input Low Voltage, VINL |
0.8 |
0.8 |
0.8 |
V max |
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Input Current |
±10 |
±10 |
±10 |
μA max |
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IIN (Data Inputs) |
VIN = 0 V to VDD |
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Input Capacitance6 |
8 |
8 |
8 |
pF max |
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ANALOG OUTPUTS |
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kΩ min/max |
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Output Range Resistors |
15/30 |
15/30 |
15/30 |
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Output Voltage Ranges7 |
+5, +10 |
+5, +10 |
+5, +10, ±5 |
V |
Single Supply; (VSS = 0 V) |
Output Voltage Ranges7 |
+5, +10, ±5 |
+5, +10, ±5 |
Ω typ |
Dual Supply; (VSS = –12 V to –15 V4) |
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DC Output Impedance |
0.5 |
0.5 |
0.5 |
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AC CHARACTERISTICS6 |
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Settling Time to Within ±1/2 LSB of Final Value |
Voltage Output Settling Time |
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μs max |
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Positive Full-Scale Change |
8 |
8 |
10 |
DAC Latch all 0s to all 1s. Typically 5 μs |
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Negative Full-Scale Change |
8 |
8 |
10 |
μs max |
DAC Latch all 1s to all 0s. Typically 5 μs |
Digital-to-Analog Glitch |
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VSS = –12 V to –15 V4. |
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Impulse3 |
30 |
30 |
30 |
nV secs typ |
DAC Latch Contents Toggled Between all 0s and all 1s |
Digital Feedthrough3 |
10 |
10 |
10 |
nV secs typ |
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Digital Crosstalk3 |
30 |
30 |
30 |
nV secs typ |
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POWER REQUIREMENTS |
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VDD |
+10.8/+16.5 |
+11.4/+15.75 |
+11.4/+15.75 |
V min/max |
For Specified Performance Unless Otherwise Stated |
VSS |
–10.8/–16.5 |
–11.4/–15.75 |
–11.4/–15.75 |
V min/max |
For Specified Performance Unless Otherwise Stated |
IDD |
15 |
15 |
15 |
mA max |
Output Unloaded. Typically 10 mA |
ISS (Dual Supplies) |
5 |
5 |
5 |
mA max |
Output Unloaded. Typically 3 mA |
NOTES
1Power Supply tolerance is ±10% for A version and ±5% for B and T versions.
2Temperature ranges are as follows: A, B Versions, –40°C to +85°C; T Version, –55°C to +125°C. 3See Terminology.
4With appropriate power supply tolerances.
5Measured with respect to REF IN and includes unipolar/bipolar offset error. 6Sample tested @ +25°C to ensure compliance.
70 V to +10 V range is only available with VDD ³ 14.25 V.
Specifications subject to change without notice.
–2– |
REV. 0 |
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AD7237A/AD7247A |
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TIMING CHARACTERISTICS1, 2 |
(VDD = +12 V to +15 V,3 VSS = 0 V or –12 V to –15 V,3 AGND = DGND = 0 V [AD7237A], |
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GND = 0 V [AD7247A]) |
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Limit at TMIN, TMAX |
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Limit at TMIN, TMAX |
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Parameter |
(A, B Versions) |
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(T Version) |
Units |
Conditions/Comments |
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t1 |
0 |
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0 |
ns min |
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to |
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Setup Time |
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CS |
WR |
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t2 |
0 |
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0 |
ns min |
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CS |
to |
WR |
Hold Time |
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t3 |
80 |
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100 |
ns min |
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WR Pulse Width |
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t4 |
80 |
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80 |
ns min |
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Data Valid to |
WR |
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Setup Time |
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t54 |
10 |
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10 |
ns min |
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Data Valid to |
WR |
Hold Time |
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t6 |
0 |
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0 |
ns min |
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Address to WR Setup Time |
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t7 |
0 |
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0 |
ns min |
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Address to |
WR |
Hold Time |
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t85 |
80 |
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100 |
ns min |
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LDAC |
Pulse Width |
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 5 and 7.
3Power Supply tolerance is ±10% for A version and ±5% for B and T versions. 4If 0 ns < t2 < 10 ns, add t2 to t5. If t2 ³ 10 ns, add 10 ns to t5.
5AD7237A only.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted) |
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VDD to GND (AD7247A) . . . . . . . . . . . . . |
. . . –0.3 V to +17 V |
VDD to AGND, DGND (AD7237A) . . . . . |
. . . –0.3 V to +17 V |
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . –0.3 V to +34 V |
AGND to DGND (AD7237A) . . . . . . . . . |
–0.3 V, VDD +0.3 V |
VOUTA,2 VOUTB2 to AGND (GND) . . VSS –0.3 V to VDD +0.3 V
REF OUT to AGND (GND) . . . . . . . . |
. . . . |
. . . . . 0 V to VDD |
REF IN to AGND (GND) . . . . . . . . . . |
–0.3 V to VDD +0.3 V |
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Digital Inputs to DGND (GND) . . . . . . |
–0.3 V to VDD +0.3 V |
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Operating Temperature Range |
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–40°C to +85°C |
Industrial (A, B Versions) . . . . . . . . . . |
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Extended (T Version) . . . . . . . . . . . . . |
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–55°C to +125°C |
Storage Temperature Range . . . . . . . . . . |
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–65°C to +150°C |
Lead Temperature (Soldering, 10 secs) . . |
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. . . . . . . +300°C |
Power Dissipation (Any Package) to +75°C . . |
. . . . . 1000 mW |
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Derates above +75°C by . . . . . . . . . . . . . |
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. . . . . 10 mW/°C |
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2Short-circuit current is typically 80 mA. The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded.
ORDERING GUIDE
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Relative |
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Temperature |
Accuracy |
Package |
Model1 |
Range |
(LSB) |
Option2 |
AD7237AAN |
–40°C to +85°C |
±1 max |
N-24 |
AD7237ABN |
–40°C to +85°C |
±1/2 max |
N-24 |
AD7237AAR |
–40°C to +85°C |
±1 max |
R-24 |
AD7237ABR |
–40°C to +85°C |
±1/2 max |
R-24 |
AD7237ATQ |
–55°C to +125°C |
±1/2 max |
Q-24 |
AD7247AAN |
–40°C to +85°C |
±1 max |
N-24 |
AD7247ABN |
–40°C to +85°C |
±1/2 max |
N-24 |
AD7247AAR |
–40°C to +85°C |
±1 max |
R-24 |
AD7247ABR |
–40°C to +85°C |
±1/2 max |
R-24 |
AD7247ATQ |
–55°C to +125°C |
±1/2 max |
Q-24 |
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact local sales office for military data sheet and availability.
2N = Plastic DIP; Q = Cerdip; R = Small Outline (SOIC).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7237A/AD7247A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0 |
–3– |
AD7237A/AD7247A
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AD7237A PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS) |
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Pin |
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Mnemonic |
Description |
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1 |
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REF INA |
Voltage Reference Input for DAC A. The reference voltage for DAC A is applied to this pin. It is internally |
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buffered before being applied to the DAC. The nominal reference voltage for correct operation of the |
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AD7237A is 5 V. |
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REF OUT |
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part with |
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internal reference, REF OUT should be connected to REF INA, REF INB. |
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REF INB |
Voltage Reference Input for DAC B. The reference voltage for DAC B is applied to this pin. It is internally |
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buffered before being applied to the DAC. The nominal reference voltage for correct operation of the |
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AD7237A is 5 V. |
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ROFSB |
Output Offset Resistor for DAC B. This input configures the output ranges for DAC B. It is connected to |
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VOUTB for the +5 V range, to AGND for the +10 V range and to REF INB for the ±5 V range. |
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VOUTB |
Analog Output Voltage from DAC B. This is the buffer amplifier output voltage. Three different output |
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voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and ±5 V. The amplifier is capable of developing |
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+10 V across a 2 kΩ resistor to GND. |
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AGND |
Analog Ground. Ground reference for DACs, reference and output buffer amplifiers. |
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7 |
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DB7 |
Data Bit 7. |
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8-10 |
DB6-DB4 |
Data Bit 6 to Data Bit 4. |
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11 |
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DB3 |
Data Bit 3/Data Bit 11 (MSB). |
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12 |
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DGND |
Digital Ground. Ground reference for digital circuitry. |
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13 |
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DB2 |
Data Bit 2/Data Bit 10. |
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14 |
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DB1 |
Data Bit 1/Data Bit 9. |
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15 |
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DB0 |
Data Bit 0 (LSB)/Data Bit 8. |
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16 |
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A0 |
Address Input. Least significant address input for input latches. A0 and A1 select which of the four input |
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latches data is written to (see Table II). |
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17 |
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A1 |
Address Input. Most significant address input for input latches. |
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18 |
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Chip Select. Active low logic input. The device is selected when this input is active. |
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CS |
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19 |
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Write Input. |
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is an active low logic input which is used in conjunction with |
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, A0 and A1 to write data |
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WR |
WR |
CS |
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to the input latches. |
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20 |
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Load DAC. Logic input. A new word is loaded into the DAC latches from the respective input latches on the |
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LDAC |
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falling edge of this signal. |
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VDD |
Positive Supply (+12 V to +15 V). |
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22 |
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VOUTA |
Analog Output Voltage from DAC A. This is the buffer amplifier output voltage. Three different output |
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voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and ±5 V. The amplifier is capable of developing |
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+10 V across a 2 kΩ resistor to GND. |
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VSS |
Negative Supply (0 V or –12 V to –15 V). |
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24 |
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ROFSA |
Output Offset Resistor for DAC A. This input configures the output ranges for DAC A. It is connected to |
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VOUTA for the +5 V range, to AGND for the +10 V range and to REF INA for the ±5 V range. |
–4– |
REV. 0 |