Texas Instruments TPS77333DGKR, TPS77333DGK, TPS77328DGKR, TPS77328DGK, TPS77327DGKR Datasheet

TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS281A ± FEBRUARY 2000 ± REVISED MARCH 2000

D Open Drain Power-On Reset With 220-ms							TPS773xx
Delay (TPS773xx)							DGK PACKAGE
							(TOP VIEW)
D Open Drain Power-Good (PG) Status	FB/SENSE									OUT
						1	8
Output (TPS774xx)
	RESET					2	7			OUT
D 250-mA Low-Dropout Voltage Regulator
		EN				3	6			IN
D Available in 1.8-V, 2.7-V, 2.8-V, 3.3-V, Fixed		GND				4	5			IN
Output and Adjustable Versions

DDropout Voltage Typically 200 mV at 250 mA (TPS77333, TPS77433)

DUltra Low 92- A Quiescent Current (Typ)

D8-Pin MSOP (DGK) Package

DLow Noise (55 Vrms) Without an External

Filter (Bypass) Capacitor (TPS77318, TPS77418)

D2% Tolerance Over Specified Conditions For Fixed-Output Versions

DFast Transient Response

DThermal Shutdown Protection

DSee the TPS779xx Family of Devices for Active High Enable

description

The TPS773xx and TPS774xx are low dropout regulators with integrated power-on reset and power good (PG) function respectively. These devices are capable of supplying 250 mA of output current with a dropout of 200 mV (TPS77333, TPS77433). Quiescent current is 92 A at full load dropping down to 1 A when device is disabled. These devices are optimized to be stable with a wide range of output capacitors including low ESR ceramic (10 F) or low capacitance (1 F) tantalum capacitors. These devices have extremely low noise output performance (55 Vrms) without using any added filter capacitors. TPS773xx and TPS774xx are designed to have fast transient response for larger load current changes.

TPS774xx

DGK PACKAGE

(TOP VIEW)

FB/SENSE					1	8			OUT
PG					2	7			OUT
					3	6			IN
	EN
GND					4	5			IN

TPS77x33

DROPOUT VOLTAGE vs

JUNCTION TEMPERATURE

	300
	250	IO = 250 mA
± mV	200
Voltage
	150
± Dropout
	100
DO
				IO = 10 mA
V
	50				IO = 0 A
	0				120	140
	±40	0	40	80
		TJ ± Junction Temperature ± °C

The TPS773xx or TPS774xx is offered in 1.8-V, 2.7-V, 2.8-V and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS773xx and TPS774xx families are available in 8-pin MSOP (DGK) packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

This document contains information on products in more than one phase	Copyright 2000, Texas Instruments Incorporated
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265	1

TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS281A ± FEBRUARY 2000 ± REVISED MARCH 2000

description (continued)

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV at an output current of 250 mA for 3.3 volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 A over the full range of output current, 0 mA to 250 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 A at TJ = 25°C.

The TPS773xx features an integrated power-on reset, commonly used as an supply voltage supervisor (SVS), or reset output voltage. The RESET output of the TPS773xx initiates a reset in DSP, microcomputer or microprocessor systems at power-up and in the event of an undervoltage condition. An internal comparator in the TPS773xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after a 220 ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage.

For the TPS774xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS774xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage.

AVAILABLE OPTIONS

	OUTPUT
	VOLTAGE	PACKAGED DEVICES
TJ	(V)
	TYP		MSOP
			(DGK)
	3.3	TPS77333DGK		TPS77433DGK
	2.8	TPS77328DGK		TPS77428DGK
±40°C to 125°C	2.7	TPS77327DGK		TPS77427DGK
	1.8	TPS77318DGK		TPS77418DGK
	Adjustable	TPS77301DGK		TPS77401DGK
	1.5 V to 5.5 V

The TPS77301 and TPS77401 are programmable using an external resistor divider (see application information). The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77301DGKR).

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

				SLVS281A ± FEBRUARY 2000 ± REVISED MARCH 2000
	VI	5		7	VO
		IN	OUT
		6	OUT	8
		IN
			SENSE	1
	0.1 F	3	PG or	2
		EN			PG or RESET Output
			RESET
				+
					F
			GND	10
		4

Figure 1. Typical Application Configuration (For Fixed Output Options)

functional block diagramÐadjustable version

IN
EN
	PG or RESET
_
+	OUT

	+	220 ms Delay	R1
	_	(for TPS773xx Option)
	Vref = 1.1834 V		FB/SENSE
			R2

GND

External to the device

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS281A ± FEBRUARY 2000 ± REVISED MARCH 2000

functional block diagramÐfixed-voltage version

	IN
	EN
			PG or RESET
	_
	+		OUT
	+	220 ms Delay	SENSE
			R1
	_	(for TPS773xx Option)
	Vref = 1.1834 V

R2

						GND
						Terminal Functions (TPS773xx)
			TERMINAL		I/O	DESCRIPTION
		NAME		NO.
	FB/SENSE			1	I	Feedback input voltage for adjustable device (sense input for fixed options)
				2	O	Reset output
	RESET
				3	I	Enable input
	EN
	GND			4		Regulator ground
	IN			5, 6	I	Input voltage
	OUT			7, 8	O	Regulated output voltage
						Terminal Functions (TPS774xx)
			TERMINAL		I/O	DESCRIPTION
		NAME		NO.
	FB/SENSE			1	I	Feedback input voltage for adjustable device (sense input for fixed options)
	PG			2	O	Power good
				3	I	Enable input
	EN
	GND			4		Regulator ground
	IN			5, 6	I	Input voltage
	OUT			7, 8	O	Regulated output voltage

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

				SLVS281A ± FEBRUARY 2000 ± REVISED MARCH 2000
TPS773xx RESET timing diagram
VI
Vres²				Vres
				t
VO	V	³	V	³
		IT +		IT +
Threshold
Voltage
		VIT ±³		VIT ±³
				t
RESET		220 ms		220 ms
Output
		Delay		Delay
Output				Output
Undefined				Undefined
				t

²Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.

³VIT ±Trip voltage is typically 5% lower than the output voltage (95%VO) VIT± to VIT+ is the hysteresis voltage.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS281A ± FEBRUARY 2000 ± REVISED MARCH 2000

TPS774xx PG timing diagram
VI
Vres²				Vres
				t
VO	V	³	V	³
		IT +		IT +
Threshold
Voltage
		VIT ±³		VIT ±³
				t
PG
Output

Output	Output
Undefined	Undefined
	t

²Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.

³VIT ±Trip voltage is typically 18% lower than the output voltage (82%VO) VIT± to VIT+ is the hysteresis voltage.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS281A ± FEBRUARY 2000 ± REVISED MARCH 2000

absolute maximum ratings over operating junction temperature range (unless otherwise noted)

Input voltage range³ , VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . ±0.3 V to 13.5	V
Voltage range at		EN		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±0.3 V to 16.5	V
Maximum	RESET		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .voltage (TPS773xx)		. . . . . . . . . . . . . . . . . . 16.5 V
Maximum PG voltage (TPS774xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . 16.5	V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					See dissipation rating tables
Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . 5.5	V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . ±40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . ±65°C to 150°C
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 2 kV

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ³ All voltage values are with respect to network terminal ground.

			DISSIPATION RATING TABLE ± FREE-AIR TEMPERATURES
	PACKAGE	AIR FLOW	θJA	θJC	TA < 25°C	DERATING FACTOR	TA = 70°C	TA = 85°C
		(CFM)	(°C/W) (°C/W)		POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING
		0	266.2	3.84	376 mW	3.76 mW/°C	207 mW	150 mW
	DGK	150	255.2	3.92	392 mW	3.92 mW/°C	216 mW	157 mW
		250	242.8	4.21	412 mW	4.12 mW/°C	227 mW	165 mW

recommended operating conditions

	MIN	MAX	UNIT
Input voltage, VI§	2.7	10	V
Output voltage range, VO	1.5	5.5	V
Output current, IO (see Note 1)	0	250	mA
Operating virtual junction temperature, TJ (see Note 1)	± 40	125	°C

§ To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the

device operate under conditions beyond those specified in this table for extended periods of time.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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