Texas Instruments TSB21LV03CIPM, TSB21LV03CPM, TSB21LV03CMHVB, TSB21LV03CMHV Datasheet

TSB21LV03C IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999

DFully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus

DFully Interoperable with FireWire and i.LINK Implementation of IEEE 1394-1995

DProvides Three Fully Compliant Cable Ports at 100/200 Megabits per Second (Mbits/s)

DCable Ports Monitor Line Conditions for Active Connection to Remote Node

DDevice Power-Down Feature to Conserve Energy in Battery-Powered Applications

DInactive Ports Disabled to Save Power

DLogic Performs System Initialization and Arbitration Functions

DEncode and Decode Functions Included for Data-Strobe Bit-Level Encoding

DIncoming Data Resynchronized to Local Clock

DSingle 3.3-V Supply Operation

description

DInterface to Link-Layer Controller Supports Low Cost TI Bus-Holder Isolation

DData Interface to Link-Layer Controller Provided Through 2/4 Parallel Lines at 49.152 MHz

DLow Cost 24.576-MHz Crystal Oscillator and PLL Provide Transmit/Receive Data at 100/200 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz

DInteroperable with 1394 Link-Layer Controllers Using 5-V Supplies

DInteroperable Across 1394 Cable with 1394 Physical Layers (Phy) Using 5-V Supplies

DNode Power-Class Information Signaling for System Power Management

DCable Power Presence Monitoring

DSeparate Cable Bias and Driver Termination Voltage Supply for Each Port

DHigh Performance 64-Pin TQFP (PM) Package and 68-Pin CFP (HV) Package

The TSB21LV03C provides the analog and digital physical layer functions needed to implement a three-port node in a cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB21LV03C is designed to interface with a link-layer controller (LLC), such as the TSB12LV21, TSB12LV31, TSB12C01, TSB12LV22, TSB12LV41, or TSB12LV01.

The TSB21LV03C requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The 196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. For the TSB21LV03C, the 49.152 MHz clock output is active when RESET is asserted low. The power-down function, when enabled by taking the PD terminal high, stops operation of the PLL and disables all circuitry except the cable-not-active signal circuitry.

The TSB21LV03C supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the link interface outputs behave normally. Also, when ISO is tied high, the internal bus hold function is enabled for use with the TI Bus Holder isolation. TI bus holder isolation is implemented when ISO is tied high.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FireWire is a trademark of Apple Computer, Incorporated. i.LINK is a trademark of SONY.

TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999

description (continued)

Data bits to be transmitted through the cable ports are received from the LLC on two or four data lines (D0 ± D3), and are latched internally in the TSB21LV03C in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304 or 196.608 Mbits/s as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).

During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded Strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two or four parallel streams, resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) out of the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this common-mode voltage is used as an indication of cable connection status. The cable connection status signal is internally debounced in the TSB21LV03C on a cable disconnect-to-connect. The debounced cable connection status signal initiates a bus reset. On a cable disconnect-to-connect a debounce delay is incorporated. There is no delay on a cable disconnect.

The TSB21LV03C provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from either 5-V or 3-V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of approximately 1.0 µF.

The transmitter circuitry is disabled under the following conditions: power down, cable not active, reset, or transmitter disable. The receiver circuitry is disabled under the following conditions: power down, cable not active, or receiver disable. The twisted-pair bias voltage circuitry is disabled under the following conditions: power down or reset. The power-down condition occurs when the PD input is high. The cable-not-active (CNA) condition occurs when the cable connection status indicates that no cable is connected. The reset condition occurs when the RESET input terminal is low. The transmitter disable and receiver disable conditions are determined from the internal logic.

The line drivers in the TSB21LV03C operate in a high-impedance current mode and are designed to work with external 110-Ω line-termination resistor networks. One network is provided at each end of each twisted-pair cable. Each network is composed of a pair of series-connected 55-Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A (TPA) package terminals is connected to the TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B (TPB) package terminals is coupled to ground through a parallel RC network with recommended resistor and capacitor values of 5 kΩ and 220 pF respectively. The values of the external resistors are designed to meet the draft standard specifications when connected in parallel with the internal receiver circuits and are shown in Figure 3.

The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between the R0 and R1 terminals and has a value of 6.3 kΩ, ±0.5%. This might be accomplished by placing a 6.34 kΩ, ±0,5% resistor in parallel with a 1-MΩ resistor.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999

description (continued)

Four package terminals are used as inputs to set four configuration status bits in the self-identification (Self-ID) packet. These terminals are hardwired high or low as a function of the equipment design. PC0 ± PC2 are the three terminals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth terminal, C/LKON, indicates whether a node is a contender for bus manager. When the C/LKON terminal is asserted, it means the node can be a contender for bus manager. When the terminal is not asserted, it means that the node is not a contender. The C bit corresponds to bit 20 in the Self-ID packet, PC0 corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23 (see Table 4±29 of the IEEE 1394±1995 standard for additional details).

A power-down terminal, PD, is provided to allow a power-down mode where most of the TSB21LV03C circuits are powered down to conserve energy in battery-powered applications. A cable status terminal, CNA, provides a high output when all twisted-pair cable ports are disconnected. This output is not debounced. The CNA output can be used to determine when to power the TSB21LV03C down or up. In the power-down mode all circuitry is disabled except the CNA circuitry. It should be noted that when the device is powered-down it does not act in a repeater mode. When the TSB21LV03C is powered down using the PD terminal, the twisted-pair transmitter and receiver circuitry has been designed to present a high impedance to the cable to prevent loading the TPBias terminal voltage on the other end of the cable.

NOTE:

Reference suspend/resume section in the current 1394a specification for interoperability with PD implementation of power down.

If the TSB21LV03C is being used with one or more of the ports not being brought out to a connector, the TPB terminals must be terminated for reliable operation. For each unused port, the TPB+ and TPB± terminals must be connected to GND. This is done in the normal termination network. When a port does not have a cable connected, the normal termination network pulls TPB+ and TPB± to ground through a 5-kΩ resistor, thus disabling the port.

NOTE:

All gap counts on all nodes of a 1394 bus must be identical. This may only be accomplished by using phy configuration packets (see section 4.3.4.3 of IEEE 1394-1995 Standard) or by using two bus resets, which resets the gap counts to the maximum level (3 Fh).

The link power status (LPS) terminal works with the C/LKON terminal to manage the LLC power usage of the node. The LPS terminal indicates that the LLC of the node is powered down and powers down the phy-LLC interface to save power. If the phy then receives a link-on packet, the C/LKON terminal is activated to output a 6.114 MHz signal, which can be used by the LLC to power itself up. Once the LLC is powered up, the LPS signal communicates this to the TSB21LV03C and the C/LKON signal is turned off and the phy-link interface is enabled.

Two of the package terminals are used to set up various test conditions used in manufacturing. These terminals, TESTM1 and TESTM2, should be connected to VDD for normal operation.

The TSB21LV03C is characterized for operation from 0°C to 70°C. The TSB21LV03CI is characterized for operation from ±40°C to 85°C. The TSB21LV03CM is characterized for operation over the full military temperature range of ±55°C to 125°C.

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3

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999

functional block diagram

CPS		Received
LPS		Data
ISO		Decoder/	Bias
CNA		Retimer
SYSCLK			Voltage
			and
LREQ	Link
			Current
CTL0	Interface		Generator
CTL1	I/O
D0
D1
D2		Arbitration
D3
		and
		Control
PC0		State	Cable Port 1
		Machine
PC1
		Logic
PC2
C/LKON
TESTM1
TESTM2
PD			Cable Port 2
		Transmit
		Data
RESET		Encoder
			Cable Port 3
			Crystal
			Oscillator,
			PLL
			System, and
			Clock
			Generator

R0

R1

TPBIAS1

TPBIAS2

TPBIAS3

TPA 1+ TPA1 ±

TPB1 + TPB1 ±

TPA2 +

TPA2 ± TPB2 +

TPB2 ±

TPA3 + TPA3 ± TPB3 + TPB3 ±

XI

XO FILTER

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999

package outline

PLASTIC QUAD FLATPACK (PM)

(TOP VIEW)

DGND

DGND

ISO

AGND

R1

R0

PLLV

XO

XI AV FILTER

PLLGND

PLLGND

AV

AGND

AGND

DD

DD

DD

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RESET

TPBIAS3

1

48

LPS

2

47

TPBIAS2

LREQ

3

46

TPBIAS1

VDD-5V

4

45

TPA1+

DVDD

5

44

TPA1±

DVDD

6

43

TPB1+

PD

7

42

TPB1±

DGND

8

TSB21LV03C

41

AGND

SYSCLK

9

40

TPA2+

DGND

10

39

TPA2±

CTL0

11

38

TPB2+

CTL1

12

37

TPB2±

D0

13

36

TPA3+

D1

14

35

TPA3±

D2

15

34

TPB3+

D3

16

19 20 21 22 23 24 25 26 27 28

29 30 31

33

TPB3±

17 18

32

DGND

DGND

DV

DV

TESTM2

TESTM1

CPS

AV

AV AGND C/LKON

PC2

PC1

PC0

CNA

AGND

DD

DD

DD

DD

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5

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999

CERAMIC QUAD FLATPACK (HV) (TOP VIEW)

DGND

DGND

ISO

AGND

AGND

R1

R0

DD

X0

X1

DD

FILTER

PLLGND PLLGND

DD

AGND

AGND

PLLV

AV

AV

RESET

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

TPBIAS3

10

60

LPS

11

59

TPBIAS2

LREQ

12

58

TPBIAS1

VDD±5V

13

57

TPA1+

DVDD

14

56

TPA1±

DVDD

15

55

TPB1+

PD

16

54

TPB1±

DGND

17

53

AGND

DGND

18

52

AGND

SYSCLK

19

51

TPA2+

DGND

20

50

TPA2±

CTL0

21

49

TPB2+

CTL1

22

48

TPB2±

D0

23

47

TPA3+

D1

24

46

TPA3±

D2

25

45

TPB3+

D3

26

44

TPB3±

27

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

DGND

DGND

DD

DD

TESTM2

TESTM1

CPS

DD

DD

AGND

AGND

C/LKON

PC2 PC1

PC0

CNA

AGND

DV

DV

AV

AV

AVAILABLE OPTIONS

		PACKAGE
	TA	PLASTIC QUAD	CERAMIC QUAD
		FLAT PACK	FLAT PACK
		(PM)	(HV)
	0°C to 70°C	TSB21LV03CPM	Ð
	± 40°C to 85°C	TSB21LV03CIPM	Ð
	± 55°C to 125°C	Ð	TSB21LV03CMHVB

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

					SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999
				Terminal Functions
	TERMINAL
			TYPE	I/O	DESCRIPTION
NAME	NO.
	HV	PM
AGND	5, 6, 36,	26, 32, 41,	Supply	Ð	Analog circuit ground. All AGND terminals should be tied together to the
	37, 43, 52,	49, 50, 61			low-impedance circuit-board ground plane. External to the device, AGND
	53, 61, 62				should be tied to DGND and PLLGND.
AVDD	34, 35,	24, 25,	Supply	Ð	Analog circuit power. A combination of high frequency decoupling capacitors
	63, 67	51, 55			near each AVDD terminal is suggested, such as 0.1-µF and 0.001-µF capacitors.
					Lower frequency 10-µF filtering capacitors are also recommended. AVDD
					terminals are separated from DVDD terminals internally from the other supply
					terminals to provide noise isolation. They should be tied together to a power
					plane on the circuit board. Each supply source should be individually filtered.
C/LKON	38	27	CMOS	I/O	Bus manager capable (input). When set as an input, C/LKON specifies in the
					Self-ID packet that the node is bus manager capable. The bit value programming
					is done by tying the terminal through a 10-kΩ resistor to VDD (high, bus manager
					capable) or to GND (low, not bus manager capable). Using either the pullup or
					pulldown resistor allows the LINK ON output to override the input bit value when
					necessary.
					Link-on (output). When set as an output, C/LKON indicates the reception of a
					link-on message by asserting a 6.114-MHz signal.
CNA	42	31	CMOS	O	Cable-not-active output. CNA is asserted high when none of the TSB21LV03C
					ports are connected to another active port. This circuit remains active during the
					power-down mode.
CPS	33	23	CMOS	I	Cable power status. CPS is normally connected to the cable power through a
					400-kΩ resistor. This circuit drives an internal comparator that detects the
					presence of cable power. This information is maintained in two internal registers
					and is available to the LLC by way of a register read (see the Phy-Link Interface
					Annex in the IEEE 1394-1995 standard).
CTL0	21	11	CMOS	I/O	Control I/O. The CTLn terminals are bidirectional communications control
CTL1	22	12			signals between the TSB21LV03C and the LLC. These signals control the
					passage of information between the two devices. Control I/O terminals are 5-V
					tolerant. The CTLn terminals have an internal bus-holder function built-in.
D0 ± D3	23, 24,	13, 14,	CMOS	I/O	Data I/O. The D terminals are bidirectional and pass data between the
	25, 26	15, 16			TSB21LV03C and the LLC. Data I/O terminals are 5-V tolerant. The D terminals
					have an internal bus-holder function built-in.
DGND	8, 9, 17,	8, 10, 17,	Supply	Ð	Digital circuit ground. The DGND terminals should be tied to the low-impedance
	18, 20,	18, 63, 64			circuit-board ground plane. External to the device, AGND should be tied to
	27, 28				DGND and PLLGND.
DVDD	14, 15,	5, 6,	Supply	Ð	Digital circuit power. DVDD supplies power to the digital portion of the device. It is
	29, 30	19, 20			recommended that a combination of high-frequency decoupling capacitors be
					connected to DVDD (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency
					10-µF filtering capacitors can also be used. These supply terminals are
					separated from AVDD internally in the device to provide noise isolation. These
					terminals should also be tied together to a power plane on the circuit board.
					Individual filtering networks for each is desired.
FILTER	66	54	CMOS	I/O	PLL filter. FILTER is connected to a 0.1-µF capacitor and then to PLLGND to
					complete the internal lag-lead filter. This filter is required for stable operation of
					the frequency multiplier PLL running off of the crystal oscillator.

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7

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999

Terminal Functions (Continued)

TERMINAL

TYPE

I/O

DESCRIPTION

NAME

NO.

HV

PM

7

62

CMOS

I

Link interface isolation input.

is normally tied high both to implement TI

ISO

ISO

bus-holder isolation or no isolation. The TSB21LV03C does not support Annex J

isolation.

LPS

11

2

CMOS

I

Link power status. LPS is connected to either the VDD supplying the LLC through

a 1±k Ω resistor or directly to a pulsed output that is active when the LLC is

powered for the purpose of monitoring the LLC power status. The pulsed signal

must be between 220 kHz and 5.5 MHz to be sensed as active. If LPS is inactive,

the phy-LLC interface is disabled, and the TSB21LV03C performs only the basic

repeater functions required for network initialization and operation. LPS is 5-V

tolerant and has an internal bus-holder function built-in. If this terminal is tied

through a resistor to a fixed state, the resistor must be 1 kΩ or less.

LREQ

12

3

CMOS

I

Link request. LREQ is an input from the LLC that requests the TSB21LV03C to

perform some service. LREQ is 5-V tolerant and has an internal bus-holder

function built-in. If this terminal is tied through a resistor to a fixed state, the

resistor must be 1 kΩ or less.

PC2 ± PC0

39, 40, 41

28, 29, 30

CMOS

I

Power class indicators. The PC signals set the bit values of the three

power-class bits in the Self-ID packet (bits 21, 22, and 23). These bits can be

programmed by tying the terminals to VDD (high) or to GND (low).

PD

16

7

CMOS

I

Power down. When asserted high, PD turns off all internal circuitry except the

CNA monitor circuits that drive the CNA terminal. PD is 5-V tolerant. The PD

terminal may be tied directly to VDD or to DGND. If this terminal is tied through a

resistor to a fixed state, the resistor must be 1 kΩ or less. The PD terminal has an

internal bus-holder function built in to it.

PLL circuit ground. The PLLGND terminals should be tied to the low-impedance

PLLGND

64, 65

52, 53

Supply

Ð

circuit-board ground plane. External to the device, AGND should be tied to

DGND and PLLGND.

PLL circuit power. PLLVDD supplies power to the PLL portion of the device. It is

recommended that a combination of high-frequency decoupling capacitors be

connected

to

PLLVDD

2

58

Supply

Ð

PLLVDD (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency 10-µF filtering

capacitors can also be used. The PLLVDD supply terminals are separated from

AVDD and DVDD internally in the device to provide noise isolation. The PLLVDD,

AVDD, and DVDD terminals should also be tied together to a power plane on the

circuit board. Individual filtering networks for each is recommended.

R0

3

59

Current setting resistor. An internal reference voltage is applied to a resistor con-

Ð

Ð

nected between R0 and R1 to set the operating current and the cable driver out-

R1

4

60

put current. A resistance of 6.3 kΩ ±0.5% should be used to meet the IEEE

1394-1995 standard requirements for output voltage limits.

Reset. When

is asserted low (active), a bus reset condition is set on the

RESET

active cable ports and the the internal logic is reset to the reset start state. An

10

1

CMOS

I

internal pullup resistor, which is connected to VDD, is provided so only an exter-

RESET

nal delay capacitor is required. This input is a standard logic buffer and can also

be driven by an open-drain logic output buffer. The minimum hold time for RE-

SET is listed in the recommended operating characteristics table.

SYSCLK

19

9

CMOS

O

System clock. SYSCLK provides a 49.152-MHz clock signal, which is synchro-

nized with the data transfers to the LLC.

TESTM1

32

22

CMOS

I

Test mode control. TESTM1 and TESTM2 are used during the manufacturing

TESTM2

31

21

test and should be tied to VDD.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

						SLLS331A ± FEBRUARY 1999 ± REVISED OCTOBER 1999
				Terminal Functions (Continued)
	TERMINAL
				TYPE	I/O	DESCRIPTION
NAME	NO.
	HV		PM
TPA1+	57		45
TPA2+	51		40			Portn, port cable pair A. TPAn is the port A connection to the twisted-pair cable.
TPA3+	47		36
				Cable	O	Board traces from these terminals should be kept matched and as short as pos-
TPA1±	56		44
						sible to the external load resistors and to the cable connector.
TPA2±	50		39
TPA3±	46		35
TPB1+	55		43
TPB2+	49		38			Portn, port cable pair B. TPBn is the port B connection to the twisted-pair cable.
TPB3+	45		34
				Cable	O	Board traces from these terminals should be kept matched and as short as pos-
TPB1±	54		42
						sible to the external load resistors and to the cable connector.
TPB2±	48		37
TPB3±	44		33
TPBIAS1	58		46			Portn, twisted-pair bias. TPBIASn provides the 1.86-V nominal bias voltage
TPBIAS2	59		47	Cable	O	needed for proper operation of the twisted-pair cable drivers and receivers and
TPBIAS3	60		48			for sending a valid cable connection signal to the remote nodes.
						5-VVDDsupply.VDD±5VshouldbeconnectedtotheLLCVDDsupplywhena5-V
VDD±5V	13		4	Supply	Ð	LLC is connected to the phy, and it should be connected to the phy DVDD when a
						3-V LLC is used.
						Crystal oscillator. XO and XI connect to a 24.576-MHz parallel resonant funda-
XI	68		56			mental mode crystal. Although, when a 24.576-MHz crystal oscillator is used, it
				Ð	Ð	can be connected to XI with XO left unconnected. The optimum values for the
XO	1		57
						external shunt capacitors are dependent on the specifications of the crystal
						used. See application note on crystal oscillator.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V to VDD+0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V to VDD+0.5V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature, TA, TSB21LV03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TSB21LV03CI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40°C to 85°C

TSB21LV03CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±55°C to 125°C

Junction temperature, TJ, PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C HV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGE	TA ≤ 25°C	DERATING FACTOR³	TA = 70°C	TA = 85°C	TA = 125°C
	POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING	POWER RATING
PM	1866 mW	14.9 mW/_C	1194 mW	972 mW	Ð
HV	2943 mW	21.02 mW/_C	1997 mW	1681 mW	841 mW

³This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA) and uses a board-mounted 67°C/W for PM package and 47.57°C/W for HV package.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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