Loading...TEXAS INSTRUMENTS UC1525A, UC1527A, UC2525A, UC2527A, UC3525A Technical data
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UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
www.ti.com
SLUS191C–FEBRUARY 1997–REVISED JANUARY 2008
REGULATING PULSE WIDTH MODULATORS
FEATURES
∙8-V to 35-V Operation
∙5.1-V Reference Trimmed to 1%
∙100-Hz to 500-kHz Oscillator Range
∙Separate Oscillator Sync Terminal
∙Adjustable Deadtime Control
∙Internal Soft-Start
∙Pulse-by-Pulse Shutdown
∙Input Undervoltage Lockout With Hysteresis
∙Latching PWM to Prevent Multiple Pulses
∙Dual Source/Sink Output Drivers
DESCRIPTION
The UC1525A/1527A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1-V reference is trimmed to 1% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands.
BLOCK DIAGRAM
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VREF |
OSC |
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OUT |
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16 |
4 |
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+VIN |
15 |
Reference |
UVLO |
NOR |
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Regulator |
Lockout |
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GROUND |
12 |
To Internal |
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SYNC |
3 |
Circutry |
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RT |
6 |
OSC |
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Flip |
NOR |
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5 |
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Flop |
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CT |
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DISCHARGE 7 |
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UC1525A |
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Output Stage |
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COMP |
R |
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S |
OR |
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COMPENSATION 9 |
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PWM |
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Error |
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VREF |
Latch |
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INV INPUT |
1 |
Amp |
S |
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NI INPUT |
2 |
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50 mA |
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SOFTSTART 8 |
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OR |
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3 kW |
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SHUTDOWN 10
5 kW
UC1527A
Output Stage
13 VC
11 OUTPUT A
14 OUTPUT B
13 VC
11 OUTPUT A
14 OUTPUT B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. |
Copyright © 1997–2008, Texas Instruments Incorporated |
Products conform to specifications per the terms of the Texas |
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Instruments standard warranty. Production processing does not |
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necessarily include testing of all parameters. |
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UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
www.ti.com
SLUS191C–FEBRUARY 1997–REVISED JANUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (continued)
These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR logic which results in a HIGH output level when OFF.
ABSOLUTE MAXIMUM RATINGS(1)
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UCx52xA |
UNIT |
+VIN |
Supply voltage |
40 |
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VC |
Collector supply voltage |
40 |
V |
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Logic inputs |
–0.3 to +5.5 |
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Analog inputs |
–0.3 to +VIN |
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Output current, source or sink |
500 |
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Reference output current |
50 |
mA |
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Oscillator charging current |
5 |
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Power dissipation at TA = +25°C(2) |
1000 |
mW |
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Power dissipation at TC = +25°C(2) |
2000 |
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Operating junction temperature |
–55 to 150 |
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Storage temperature range |
–65 to 150 |
°C |
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Lead temperature (soldering, 10 seconds) |
300 |
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(1)Values beyond which damage may occur.
(2)See Thermal Characteristics table.
RECOMMENDED OPERATING CONDITIONS(1)
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MIN |
MAX |
UNIT |
+VIN |
Input voltage |
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8 |
35 |
V |
VC |
Collector supply voltage |
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4.5 |
35 |
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Sink/source load current (steady state) |
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0 |
100 |
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Sink/source load current (peak) |
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0 |
400 |
mA |
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Reference load current |
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0 |
20 |
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Oscillator frequency range |
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100 |
400 |
Hz |
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Oscillator timing resistor |
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2 |
150 |
kΩ |
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Oscillator timing capacitorm |
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0.001 |
0.01 |
μF |
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Dead time resistor range |
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0 |
500 |
Ω |
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UC1525A, UC1527A |
–55 |
125 |
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Operating ambient temperature range |
UC2525A, UC2527A |
–25 |
85 |
°C |
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UC3525A, UC3527A |
0 |
70 |
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(1)Range over which the device is functional and parameter limits are assured.
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Submit Documentation Feedback |
Copyright © 1997–2008, Texas Instruments Incorporated |
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Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A |
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UC1525A, UC1527A UC2525A, UC2527A
UC3525A, UC3527A
www.ti.com
SLUS191C–FEBRUARY 1997–REVISED JANUARY 2008
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PACKAGE |
θJA |
θJC |
J-16 |
80-120 |
28 |
N-16 |
90 |
45 |
DW-16 |
45-90 |
25 |
PLCC-20 |
43-75 |
34 |
LCC-20 |
70-80 |
20 |
CONNECTION DIAGRAMS |
PLCC-20, LCC-20 |
Q AND L PACKAGES |
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DIL-16 |
(TOP VIEW) |
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J or N PACKAGE |
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InputNI |
INVInput |
NC |
V |
+V |
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(TOP VIEW) |
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REF |
IN |
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INV Input |
1 |
16 |
VREF |
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NI Input |
2 |
15 |
+VIN |
SYNC |
3 |
2 |
1 |
20 19 |
Output B |
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SYNC |
3 |
14 |
Output B |
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4 |
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18 |
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OSC Output |
4 |
13 |
VC |
OSC Output |
5 |
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17 |
VC |
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CT |
5 |
12 |
Ground |
NC |
6 |
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16 |
NC |
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RT |
6 |
11 |
Output A |
CT |
7 |
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15 |
Ground |
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Discharge |
7 |
10 |
Shutdown |
RT |
8 |
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14 |
Output A |
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Soft Start |
8 |
9 |
Compensation |
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9 |
10 11 12 13 |
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Discharge |
Soft Start |
NC |
Compensation |
Shutdown |
NC − No internal connection
Copyright © 1997–2008, Texas Instruments Incorporated |
Submit Documentation Feedback |
3 |
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A |
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UC1525A, UC1527A |
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UC2525A, UC2527A |
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UC3525A, UC3527A |
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www.ti.com |
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SLUS191C–FEBRUARY 1997–REVISED JANUARY 2008 |
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ELECTRICAL CHARACTERISTICS |
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+VIN = 20 V, and over operating temperature, unless otherwise specified, TA = TJ |
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
REFERENCE |
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Output voltage |
UC152xA, UC252xA |
5.05 |
5.10 |
5.15 |
V |
TJ = 25°C |
5.0 |
5.1 |
5.2 |
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UC352xA |
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Line regulationg |
VIN = 8 V to 35 V |
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10 |
20 |
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Load regulationg |
IL = 0 mA to 20 mA |
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20 |
50 |
mV |
Temperature stability(1) |
Over operating range |
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20 |
50 |
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Total output variation(1) |
UC152xA, UC252xA |
5.0 |
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5.2 |
V |
Line, load, and temperature |
4.95 |
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5.25 |
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UC352xA |
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Shorter circuit current |
VREF = 0, TJ = 25°C |
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80 |
100 |
mA |
Output noise Voltage(1) |
10 Hz ≤ 10 kHz, T = 25°C |
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40 |
200 |
μVrms |
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J |
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Long term stability (1) |
T = 125°C |
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20 |
50 |
mV |
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J |
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OSCILLATOR SECTION(2) |
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Initial accuracy(1) (2) |
TJ = 25°C |
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2% |
6% |
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Voltage stability(1) (2) |
UC152xA, UC252xA |
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0.3% |
1% |
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VIN = 8 V to 35 V |
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1% |
2% |
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UC352xA |
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Temperature stability(1) |
Over operating range |
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3% |
6% |
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Minimum frequency |
RT = 200 kΩ, CT = 0.1 μF |
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120 |
Hz |
Maximum frequency |
RT = 2 kΩ, CT = 470 pF |
400 |
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kHz |
Current mirror |
IRT = 2 mA |
1.7 |
2.0 |
2.2 |
mA |
Clock amplitude(1) (2) |
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3.0 |
3.5 |
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V |
Clock width(1) (2) |
TJ = 25°C |
0.3 |
0.5 |
1.0 |
μs |
Syncronization threshold(1) |
(2) |
1.2 |
2.0 |
2.8 |
V |
Sync input current |
Sync voltage = 3.5 V |
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1.0 |
2.5 |
mA |
ERROR AMPLIFIER SECTION (VCM = 5.1 V) |
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Input offset voltage |
UC152xA, UC252xA |
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0.5 |
5 |
mV |
UC352xA |
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2 |
10 |
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Input bias current |
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1 |
10 |
μA |
Input offset current |
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1 |
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DC open loop gain |
RL ≥ 10 MΩ |
60 |
75 |
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dB |
Gain-bandwidth product(1) |
AV = 0 dB, TJ = 25°C |
1 |
2 |
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MHz |
DC transconductanc(1) (3) |
TJ = 25°C, 30 kΩ ≤ RL ≤ 1 MΩ |
1.1 |
1.5 |
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mS |
Low-level output voltage |
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0.2 |
0.5 |
V |
High-level output voltage |
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3.8 |
5.6 |
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Common mode rejection |
VCM = 1.5 V to 5.2 V |
60 |
75 |
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dB |
Supply voltage rejection |
VIN = 8 V to 35 V |
50 |
60 |
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(1)These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
(2)Tested at fOSC = 40 kHz (RT = 3.6 kΩ, CT = 0.01 μF, RD = 0. Approximate oscillator frequency is defined by:
f + 1 CT 0.7RT ) 3RD
(3)DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV = gMRL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum AV when the error amplifier output is loaded.
4 |
Submit Documentation Feedback |
Copyright © 1997–2008, Texas Instruments Incorporated |
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A
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